RISC-V Cores

Note: Linux를 실행하기 위해서는 현재로서는 RV64GC 및 virtual memory를 지원해야 함

rocket-core

github

ISA : RV64GC
Pipelining Stage : 5
HDL : Chisel

riscv-boom

github docs

ISA : RV64GC
Pipelining Stage : 10
HDL : Chisel

cva6

github docs

ISA : RV64GC
Pipelining Stage : 6
HDL : System Verilog

ibex

github docs

ISA : RV32EC, RV32IMC, RV32IMCB
Pipelining Stage : 3
HDL : System Verilog

riscv-mini

github

ISA : RV32I
Pipelining Stage : 3
HDL : Chisel

riscv-sodor

github

ISA : RV32I
Pipelining Stage : 1-5
HDL : Chisel

SoC Design Framework

Chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

github docs

Design Verification

riscv-dv

Random instruction generator for RISC-V processor verification

github docs

riscv-formal

RISC-V Formal Verification Framework

github docs

riscv-torture

RISC-V torture test generator and framework.

github

riscv-tests

github

chisel-verify

chisel-verify에서는 assembly instruction 생성을 지원함 (RV32I)

github docs

riscv-isa-sim

Spike, a RISC-V ISA Simulator

github

Software Env

riscv-tools

RISC-V Tools (ISA Simulator and Tests)

github

freedom

freedom : github
freedom-e-sdk : github
freedom-u-sdk : github

riscv-openocd

Fork of OpenOCD that has RISC-V support

github