I wrote this post while studying the Navilos and ARM UART PL011 of RealViewPB Datasheet from ARM Developer.
UART PL011 of RealViewPB
UARTDR [Data Register]
- The data register
- The write operation initiates transmission from the UART. The data is prefixed with a start bit, appended with the appropriate parity bit (if parity is enabled), and a stop bit. The resultant word is then transmitted.
- The received data byte is read by performing reads from the UARTDR Register along with the corresponding status information. The staus information can also be read by a read of the UARTRSR/UARTECR Register
typedef union UARTDR_t
{
uint32_t all;
struct {
uint32_t DATA:8; // Read/Write data character
uint32_t FE:1; // Framing error
uint32_t PE:1; // Parity error
uint32_t BE:1; // Break error
uint32_t OE:1; // Overrun error
uint32_t reserved:20; // Reserved
} bits;
} UARTDR_t;
UARTSR/UARTECR [Status Register / Error Clear Register ]
- The receive status reigster/error clear register
- Receive status can also be read from UARTSR Register. If the status is read from this register, then the status information for break, framing, and parity corresponds to the data character read from the Data Register, UARTDR prior to reading the UARTSR Register. The status information for overrun is set immediately when an overrun condition occurs.
- A write to UARTTECR Register clears the framing, parity, break, and overrun errors. All the bits are cleared to 0 on reset.
typedef union UARTSR_t
{
uint32_t all;
struct {
uint32_t FE:1; // Framing error
uint32_t PE:1; // Parity error
uint32_t BE:1; // Break error
uint32_t OE:1; // Overrun error
uint32_t reserved:28; // Reserved, unpredictable when read
} bits;
} UARTSR_t;UARTFR [Flag Register]
- The flag register
- After reset TXFF, RXFF, and BUSY are 0, and TXFE and RXFE are 1.
typedef union UARTFR_t
{
uint32_t all;
struct {
uint32_t CTS:1; // Clear to Send.
uint32_t DSR:1; // Data set ready
uint32_t DCD:1; // Data carrier detect
uint32_t BUSY:1; // UART busy
uint32_t RXFE:1; // Receive FIFO empty
uint32_t TXFF:1; // Trasmit FIFO full
uint32_t RXFF:1; // Receive FIFO full
uint32_t TXFE:1; // Trasmit FIFO empty
uint32_t RI:1; // Ring Indicator
uint32_t reserved:23; // Reserved
} bits;
} UARTFR_t;UARTILPR [ IrDA Low-Power Counter Register]
- The irDA low-power counter reigister
- This is an 8-bit read/write register that stores the low-power divisor value used to generate the IrLPBaud16 signal by dividing down of UARTCLK.
typedef union UARTILPR_t
{
uint32_t all;
struct {
uint32_t ILPDVSR:8; // 8-bit low poser divisor value
uint32_t reserved:24; // Reserved
} bits;
} UARTILPR_t;UARTIBRD [Integer Baud Rate Register]
- The integer part of the baud rate divisor value
typedef union UARTIBRD_t
{
uint32_t all;
struct {
uint32_t BAUDDIVINT:16; // The integer baud rate divisor
uint32_t reserved:16; // Reserved
} bits;
} UARTIBRD_t;UARTFBRD [Fractional Baud Rate Register]
- The fractional part of the baud rate divisor value
typedef union UARTFBRD_t
{
uint32_t all;
struct {
uint32_t BAUDDIVFRAC:6; // The fractional baud rate divisor
uint32_t reserved:26; // Reserved
} bits;
} UARTFBRD_t;UARTLCR_H [Line Control Register]
- The line control register
- This register accesses bits 29 to 22 of the UART Line Control Register, UARTCLR.
typedef union UARTCLR_H_t
{
uint32_t all;
struct {
uint32_t BRK:1; // Send break
uint32_t PEN:1; // Parity enable
uint32_t EPS:1; // Even Parity Select
uint32_t STP2:1; // Two stope bits select
uint32_t FEN:1; // Enable FIFOs
uint32_t WLEN:2; // Word length
uint32_t SPS:1; // Stick parity select
uint32_t reserved:24; // Reserved
} bits;
} UARTCLR_H_t;UARTCR [Control Register]
- The control register
typedef union UARTCR_t
{
uint32_t all;
struct {
uint32_t UARTEN:1; // UART enable
uint32_t SIREN:1; // SIR enable
uint32_t SIRLP:1; // SIR low-power IrDA mode
uint32_t Reserved1:4; // Reserved
uint32_t LBE:1; // Loopback enable
uint32_t TXE:1; // Transmit enable
uint32_t RXE:1; // Receive enable
uint32_t DTR:1; // Data transmit ready
uint32_t RTS:1; // Request to send
uint32_t Out1:1; // The complement of the UART Out1
uint32_t Out2:1; // The complement of the UART Out2
uint32_t RTSEn:1; // RTS hardware flow control enable
uint32_t CTSEn:1; // CTS hardware flow control enable
uint32_t reserved2:16; // Reserved
} bits;
}UARTIFLS [Interrupt FIFO Level Select Register]
- The interrupt FIFO level select register
- This register is used to define the FIFO level that triggers the assertion of UARTXINTR and UARTXINTR
typedef union UARTIFLS_t
{
uint32_t all;
struct {
uint32_t TXIFLSEL:3; // Transmit interrupt FIFO level select
uint32_t RXIFLSET:3; // Receive interrupt FIFO level select
uint32_t reserved:26; // Reserved
} bits;
} UARTIFLS_t;UARTIMSC [Interrupt Mask Set/Clear Register]
- The interrupt mask set/clear register and it is a read/write register
- On a read this register returns the current value of the mask on the relevant interrupt. On a write of 1 to the particular bit, it sets the corresponding mask of that interrupt. A write of 0 clears the corresponding mask.
typedef union UARTIMSC_t
{
uint32_t all;
struct {
uint32_t RIMIM:1; // nUARTRI modem interrupt mask for UARTRINTR
uint32_t CTSMIM:1; // nUARTCTS modem interrupt mask for UARTCTSINTR
uint32_t DCDMIM:1; // nUARTDCD modem interrupt mask for UARTDCDINTR
uint32_t DSRMIM:1; // nUARTDSR modem interrupt mask for UARTDSRINTR
uint32_t RXIM:1; // Receive interrupt mask for UARTRXINTR
uint32_t TXIM:1; // Transmit interrupt maskfor UARTTXINTR
uint32_t RTIM:1; // Receive timeout interrupt mask for UARTRTINTR
uint32_t FEIM:1; // Framing error interrupt mask for UARTFEINTR
uint32_t PEIM:1; // Parity error interrupt mask for UARTPEINTR
uint32_t BEIM:1; // Break error interrupt mask for UARTBEINTR
uint32_t OEIM:1; // Overrun error interrupt mask for UARTOEINTR
uint32_t reserved:21; // Reserved
} bits;
} UARTIMSC_t;UARTRIS [Raw Interrupt Status Register]
- The raw interrupt status register and it is a read-only register
- This register returns the current raw status value, prior to masking, of the corresponding interrupt. A write has no effect.
typedef union UARTRIS_t
{
uint32_t all;
struct {
uint32_t RIRMIS:1; // nUARTRI modem interrupt status for UARRITINTR
uint32_t CTSRMIS:1; // nUARTCTS modem interrupt status for UARTCTSINTR
uint32_t DCDRMIS:1; // nUARTDCD modem interrupt status for UARTDCDINTR
uint32_t DSRRMIS:1; // nUARTDSR modem interrupt status for UARTDSRINTR
uint32_t RXRIS:1; // Receive interrupt status for UARTRXINTR
uint32_t TXRIS:1; // Trasmit interrupt status for UARTTXINTR
uint32_t RTRIS:1; // Receive timeout interrupt status for UARTRTINTR
uint32_t FERIS:1; // Framing error interrupt status for UARTFEINTR
uint32_t PERIS:1; // Parity error interrupt status for UARTPEINTR
uint32_t BERIS:1; // Break error interrupt status for UARTBEINTR
uint32_t OERIS:1; // Overrun error interrupt status for UARTOEINTR
uint32_t reserved:21; // Reserved
} bits;
} UARTRIS_t;UARTMIS [Masked Interrupt Register]
- The masked interrupt status register and it is a read-only register.
- This register returns the current masked status value of the corresponding interrupt. A write has no effect.
typedef union UARTMIS_t
{
uint32_t all;
struct {
uint32_t RIMMIS:1; // nUARTRI modem masked interrupt status for UARTRIINTR
uint32_t CTSMMIS:1; // nUARTCTS modem masked interrupt status for UARTCTSINTR
uint32_t DCDMMIS:1; // nUARTDCD modem masked interrupt status for UARTDCDINTR
uint32_t DSRMMIS:1; // nUARTDSR modem masked interrupt status for UARTDSRINTR
uint32_t RXMIS:1; // Received masked interrupt status for UARTRXINTR
uint32_t TXMIS:1; // Transmit masked interrupt status for UARTTXINTR
uint32_t RTMIS:1; // Received timeout masked interrupt status for UARTRTINTR
uint32_t FEMIS:1; // Framing error masked interrupt status for UARTFEINTR
uint32_t PEMIS:1; // Parity error masked interrupt status for UARTPEINTR
uint32_t BEMIS:1; // Break error masked interrupt status for UARTBEINTR
uint32_t OEMIS:1; // Overrun error masked interrupt status for UARTOEINTR
uint32_t reserved:21; // Reserved
} bits;
} UARTMIS_t;UARTICR [Interrupt Clear Register]
- The interrupt clear register and is write-only
typedef union UARTICR_t
{
uint32_t all;
struct {
uint32_t RIMIC:1; // nUARTRI modem interrupt clear for UARTRIINTR
uint32_t CTSMIC:1; // nUARTCTS modem interrupt clear for UARTCTSINTR
uint32_t DCDMIC:1; // nUARTDCD modem interrupt clear for UARTDCDINTR
uint32_t DSRMIC:1; // nUARTDSR modem interrupt clear for UARTDSRINTR
uint32_t RXIC:1; // Receive interrupt clear for UARTRXINTR
uint32_t TXIC:1; // Transmit interrupt clear for UARTTXINTR
uint32_t RTIC:1; // Receive timeout interrupt clear for UARTRTINTR
uint32_t FEIC:1; // Framing error interrupt clear for UARTFEINTR
uint32_t PEIC:1; // Parity error interrupt clear for UARTPEINTR
uint32_t BEIC:1; // Break error interrupt clear for UARTBEINTR
uint32_t OEIC:1; // Overrun error interrupt clear for UARTOEINTR
uint32_t reserved:21; // Reserved
} bits;
}
UARTDMACR [DMA Control Register]
- The DMA control register is a read/write register.
- All the bits are cleared to 0 on reset.
typedef union UARTDMACR_t
{
uint32_t all;
struct {
uint32_t RXDMAE:1; // Receive DMA enable
uint32_t TXDMAE:1; // Transmit DMA enable
uint32_t DMAONERR:1; // DMA on error
uint32_t reserved:29; // Reserved
} bits;
} UARTDMACR_t;
Connecting dots