CH2: Digital Logic and Hardware Fundamental (14~23)

14. What is the difference between Combinational and Sequential logic?

• Combinational logic: Output depends only on the current inputs. There is no memory.(AND gates, Multiplexer, adders)
• Sequential logic: Output depends on the current inputs and the previous state(stored in flip-flops or latches) (counters, FSM)

always_comb begin
	y = a & b;
end

always_ff @(poesedge clk or negedge rst_n) begin
	if (!rst_n) q <= 1'b0;
    else q <= d;
end

Follow-up Q: How does a verification engineer distinguish between the two in RTL?

Combinational logic is modeled using always_comb or continuous assign statements. Sequential logic is modeled using always_ff @(posedge clk). if a designer accidentally infers a latch inside always_comb, it becomes sequential- a common bug to watch for.

15. What is a Multiplexer(Mux)? How do you build a 32:1 mux from 2:1 muxes?

A multitplexer selects one of N input signals and routes it to the output based on select signal.

// 2:1 mux
assign y = sel? b:a;

//4:1 mux using nested 2:1 muxes
assign m0 = sel[0] ? in[1]:in[0];
assign m1 = sel[0] ? in[3]:in[2];
assign y = sel[1] m1 : m0;

Building a 32 mux from 2:1 muxes:
32:1 mux requires 5 select bits ($2^5$=32). It is built as a tree of 2:1 muxes in 5 levels.

Follow-up Q: What is a " mux tree" and why does depth matter?

Each level adds propagation delay. A 32:1 Mux has 5 levels of delay. Deep mux trees can become the critical path in timing closure. In high-speed designs, pipeline registers may be inserted between levels.

16. What is a Decoder? What is the Encoder? What is a Priority Encoder?

Block	Function	Input-output	Example Use
Decoder	Converts N-bit binary to $2^N$ one-hot outputs	3 bit-> 8 lines	Address decoding, memory chip select
Encoder	Converts $2^N$ one-hot inputs to N-bit binary	8 lines -> 3 bit	Interrupt encoding
Priority Encoder	Like an encoder, but resolves conflicts when multiple inputs are active simultaneously	8 lines -> 3 bit + valid	Interrupt priority, arbiter logic

// 3 to 8 Decoder
always_comb begin
	decode = 8'b0;
    decoe[addr] = 1'b1;
end

// Priority Encoder
always_comb begin
	casez (request)
    	8'b1???????: grant = 3'd7;
        8'b01??????: grant = 3'd6;
        8'b001?????: grant = 3'd5;
        8'b0001????: grant = 3'd4;
        8'b00001???: grant = 3'd3;
        8'b000001??: grant = 3'd2;
        8'b0000001?: grant = 3'd1;
        8'b00000001: grant = 3'd0;
        default:     grant = 3'd0;
    endcase
end

Follow up Q: Why is casez used instead of case in priority encoder?

casez treats "?" as "don't care bits", allowing you to match patterens where lower-priority bits irrelevant. Using case would require listing every possible combination explicitly.

18. In RTL design, Why are Latches generally avoided while Flip-Flops are ubiquitous?

• Latches are level sensitive: They pass data transparently as long as the enable signal is active. This timing analysis extremely difficult because data can ripple through multiple latches in a single clock phase, creating unpredicatable critical paths
• Flip-Flops are edge-triggered: They only sample data on the rising (or falling) edge of a clock. This enforces strict boundaries. Data must arrive before the clock edge(Setup timem) and remain stable slightly afer (Hold time). This makes Static Timing Anaysis(STA) predictable and robust.

Trap: Are latches always bad?:
No, they are heavily used in custom datapath design, clock gating cells to save power. However they should never be inffered accidentally by a missing "else" statement in a combinational "always" block.

Follow up: How does a latch get accidentally inferred in RTL?