1. Digital Logic Design & Static Timing Analysis (STA)

Setup Time & Hold Time

A. Core Definitions (The "Stability Window")

To capture data correctly, a Flip-Flop requires the input signal to be stable during a specific window around the Clock Edge.

• Setup Time ($T_{su}$): Data must be stable BEFORE the clock edge.
• Hold Time ($T_{h}$): Data must be stable AFTER the clock edge.
• Metastability: The unstable state caused by violating $T_{su}$ or $T_{h}$

Data Path Delay = $T_{cq}$ + $T_{logic}$
$T_{cq}$: 출발지(FF)에서 나가는 데 걸리는 시간
$T_{logic}$: 중간 장애물(조합 회로)을 통과하는 시간

2. Setup Violation (Data is Too Slow)

• Problem: A Setup Violation occurs Data arrives too late.
• Equation: $T_{cq} + T_{logic} + T_{su} > T_{clk}$
• How to Fix:
  1. Lower the Clock Frequency (Increase $T_{clk}$).
  2. Optimize/Simplify Logic (Reduce $T_{logic}$).
  3. Pipelining (Add a register in the middle).

3. Hold Violation (Data is Too Fast)

• Problem: Data changes too early.
• Equation: $T_{cq} + T_{logic} < T_{h}$
• How to Fix:
  1. Add Buffers to the data path (Increase $T_{logic}$).
  2. Note: Changing clock frequency DOES NOT fix hold violations.
• "If I see a Hold Violation, I will look for paths with minimum logic and insert buffers to meet the hold requirement."

Clock Domain Crossing (CDC)

• The Problem: If you sample a signal from a different clock without synchronization, you will likely hit a Metastability state because the data might change exactly on the edge of the destination clock.

• The Solution:

  • For a single bit: Use a 2-FF Synchronizer. This gives the signal time to settle to a stable '0' or '1' over two clock cycles.

  • For multiple bits (data bus): Use an Asynchronous FIFO with Gray Code pointers. Gray code is used because only one bit changes at a time, preventing the synchronizer from seeing a "fake" value.

"How do you safely pass a signal from a 100MHz clock domain to a 200MHz clock domain?"

Finite State Machine (FSM)

• Moore Machine: The output depends only on the current state. It is generally safer as the output is synchronized with the state transitions.

• Mealy Machine: The output depends on both the current state and the inputs. It can react faster to input changes and often requires fewer states.

• FSM Encoding: One-hot encoding (one FF per state) is preferred for high-speed designs on FPGAs, while Binary encoding is more area-efficient.

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2. Computer Architecture

Pipelining & Hazards

• Structural Hazard: Resource conflict where two instructions try to use the same hardware unit simultaneously.

• Data Hazard: Occurs when an instruction depends on the result of a previous instruction that hasn't completed yet.

  • Solution: Forwarding (Bypassing) or Stalling (Bubbles).

• Control Hazard: Caused by branch instructions where the next instruction address is unknown.

  • Solution: Branch Prediction or Branch Target Buffer (BTB).

Cache Coherency (MESI Protocol)

• Modified (M): The line is present only in the current cache and is "dirty" (different from memory).

• Exclusive (E): The line is present only in the current cache and is "clean" (same as memory).

• Shared (S): The line may be stored in other caches and is "clean".

• Invalid (I): The line is invalid.

Virtual Memory & TLB

• Address Translation: Mapping Virtual Addresses (used by software) to Physical Addresses (actual RAM locations).

• TLB (Translation Lookaside Buffer): A high-speed cache used to store recent address translations to reduce the penalty of accessing Page Tables in main memory.

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3. Hardware Description Language (SystemVerilog)

Blocking (=) vs. Non-blocking (<=) Assignments

• Blocking Assignment (=): Executed sequentially in the order they appear. It is used to model Combinational Logic within an always_comb block.

• Non-blocking Assignment (<=): Scheduled to occur at the end of the time step. It is used to model Sequential Logic (Registers/Flip-Flops) within an always_ff block to avoid Race Conditions.

"Why do we use non-blocking assignments for sequential logic?"

Design Verification (DV) Concepts

OOP (Object-Oriented Programming): DV environments use Classes to create modular and reusable components like Drivers, Monitors, and Scoreboards.

• Virtual Interface: A pointer to a physical interface. It allows dynamic objects (Classes) to access static hardware modules.

• Constraint Randomization: Generating random stimuli within a legal range defined by constraints to find "corner-case" bugs.

• Functional Coverage: A user-defined metric that measures how much of the Design Specification has been exercised by the testbench.

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4. UVM

UVM Testbench Components

• Driver: It takes high-level data (Transactions) and converts them into pin-level signals (Wiggles) to talk to the Design Under Test (DUT).

• Monitor: It "watches" the pins of the DUT. It captures the activity and converts it back into Transactions to send to the Scoreboard.

• Scoreboard: This is the "Judge." It compares the output from the Monitor against the "Expected Result" (usually from a Golden Model). If they don't match, it reports an error.

Interview Question: "Can you explain the role of the Driver, Monitor, and Scoreboard in a UVM environment?"

Functional vs. Code Coverage

Interview Question: "If you have 100% Code Coverage, is your design fully verified?"

The Answer: No.

• Code Coverage: This is a quantitative metric. It tells you if every line of your Verilog code was executed. It is generated automatically by tools.

• Functional Coverage: This is a qualitative metric. You define it yourself based on the Spec. It tells you if you tested all the features and scenarios (e.g., "Did I test the FIFO when it was both Full and Empty at the same time?").

• Conclusion: You need both. Code coverage tells you what you did, and Functional coverage tells you if you did what you planned.