emmc 부팅 요약
- 전원 공급
- 초기화 단계
- CMD0 (GO_IDLE_STATE) : 이 명령은 eMMC 카드를 Idle 상태로 전환 한다. CMD0은 카드에 대한 소프트웨어 리셋을 수행하고 카드를 초기 상태로 돌린다.
- CMD1 (SEND_OP_COND) : 이 명령은 eMMC 카드에 전원이 인가되고 초기화 되었음을 알리고, 카드의 동작 상태를 확인한다.
CMD1은 반본적으로 실행되며, 카드의 동작 준비 상태가 확인 될때까지 대기합니다. - CMD2(ALL_SEND_CID) : eMMC 카드로 부터 카드 식별자 (CID)를 요청합니다. CID는 카드의 고유 식별 정보를 포함하고 있습니다.
- CMD3(SEND_RELATIVE_ADDR) : 이 명령은 eMMC 카드에 상대주소(RCA, Relative Card Address)를 할당합니다.
3 Terms and definitions
Address Space Definitions :
Mapped Host Address Space :
the area of the eMMC device that can be accessed by a read command from the host software.
Private Vendor Specific Address Space :
the area of the eMMC device that cannot be accessed by a read command from the host. It contains vendor specific internal management data.
This data can be either loaded at manufaturing or generated during device operation e.g, Memory Vendor Firmware and mapping tables. It does not contain any data(or portion of data) that was sent from the host to device.
Unmapped Host Address Space : the area of the eMMC device that cannot be accessed by a read command from the host software. It excludes private vendor specific address space. It may contain old host data or copies of host data.
Block : A number of bytes, basic data transfer unit
CID : Device IDentification register
CMD : Command line or eMMC bus command
CSD : Device Specific Data register
Data Strobe : Return Clock signal used in HS400 mode.
DISCARD : This is a performance command that allows the host to identify regions that aren't needed.
DSR : Drvier Stage Register
Empty Task Queue : A state when no tasks, ready or pending, are queue in the device's task queue.
ERASE : Block erase operation that does not require actual physical NAND erase operation.
Flash : A Type of Multiple time programmable nonvolatile memory.
Group : A number of write blocks, composite erase and write protect unit
HS200 : High Speed interface timming mode of up to 200 MB/s at 200MHz Single Date Rate Bus, 1.8V or 1.2V I/Os
HS400 : High Speed DDR interface timing mode of up to 400 MB/s at 200
RPMB : Replay Protected Memory Block
5.3 eMMC Device Overview
| Name | Width(byte) | Description | Implementation |
|---|---|---|---|
| CID | 16 | Device Identification number for identification. | Mandatory |
| RCA | 2 | Relative Device Address, is the Device system address, dynamically assigned by the host during initialization. | Mandatory |
| DSR | 2 | Driver Stage Register, to configure the Device's output drivers. | Optional |
| CSD | 16 | Device Stage Register, information about the Device operation conditions | Mandatory |
| OCR | 4 | Operation Condition Register. Used by a special broadcast command to identify the voltage type of the Device. | Mandatory |
| EXT_CSD | 512 | Extended Device Specific Data. Contains information about the Device capabilities and selected modes. Introduced in standard v4.0 |
6.3.3 Boot operation
If the CMD line is held LOW for 74 clock clycles and more after power-up or reset operation(either through CMD0 with the argument of 0xF0F0F0F0 or assertion of hardware reset for eMMC, if it is enabled in Extended CSD register byte[162], bit [1:0]) before the first commnad is issued, the slave reconginuzes that boot mode is being initiated and starts preparing boot data internally.
0xF0F0F0F0 인수를 가진 CMD0을 통해 또는 Extended CSD 레지스터 byte[162], 비트[1:0]에서 활성화된 경우 eMMC의 하드웨어 리셋 확인The partition that from the master will read the boot data can be selected in advance using EXT_CSD byte[179], bits[5:3]. The data size that the master can read during boot opertaion can be calculated as 128KB X BOOT_SIZE_MULT (EXT_CSD byte[226]). Within I second after CMD line goes LOW, the Slave starts to send the first boot data to the master on DAT line(s). The master must keep the CMD line LOW to read all of the boot data. The master must use push pull mode until boot opertaion is terminated.
. CMD 라인이 LOW 상태로 전환된 후 1초 이내에 슬레이브는 DAT 라인을 통해 마스터에게 첫 번째 부트 데이터를 보내기 시작합니다.
The master can choose to use signle data mode with backward-compatible interface timing, single data rate with high speed interface timing or dual data rate timing(if it supported) shown in 10.6 by setting a propoer value in EXT_CSD reigster byte [177] bit[4:3]. EXT_VSD reigster byte[228], bit 2 te;;s tje ,aster of tje high-speed timming during boot is supported by the device.
The master can also choose to use the dual data rate mode with interface shown in Table 208 during boot by setting "10" in EXT_CSD reigster byte[177], bits[4:3]. EXT_CSD register byte[228]. bit 1 tells the master if the dual data rate mode during boot operation.
HS200 & HS400 mode is not supported during boot opertaion
The master can choose to receive boot acknowledge from the slave by setting "1" in EXT_CSD reigster, byte[179], bit 6, so that the master can recognize that the slave is operting in boot mode.
마스터는 EXT_CSD 레지스터의 바이트 [179], 비트 6에 "1"을 설정함으로써 슬레이브로부터 부트 확인(boot acknowledge)을 수신할 수 있는 선택을 할 수 있습니다. 이렇게 하면 마스터는 슬레이브가 부트 모드로 작동하고 있음을 인식할 수 있습니다.If boot acknowledge is enabled, the slave has to send acknowledge pattern "010" to the master within 50ms after the CMD lines goes LOW. If boot acknowledge is disabled, the slave will not send out acknowledge pattern 0-1-0
In the single data rate mode, data os clocked out by the device and sampled by the host with the rising edge of the clock and there is a single CRC per data line.
In the dual data rate mode, data is clocked out with both the rising edge of the clock and the falling edge of the clock and there are two CRC appended per data line. In this mode, the block length is always 512 bytes, and bytes come interleaved in either 4-bit or 8-bit width configuration. Bytes with odd number(1,3,5,...511) shall be sampled on the rising edge of the clock by the host and bytes with even number (2,4,6,...,512) shall be sampled on the falling edge of the clokc by the host. The device will append two CRC16 per each valid data line, one corresponding to the bits of the 256 odd bytes to be sampled on the rising edge of the clock by the host and the second for the remaining bits of the 256 even bytes of the block to be sampled on the falling edge of the clock by the host.
All timings on DAT lines shall follow DDR timing mode. The start bit, the end bit and Boot acknowledge bits are only valid on the rising edge of the clock the Value of the falling edge is not guranteed.
The master can terminate boot mode with the CMD line HIGH.If the master pulls the CMD line HiGH in the middle of data transfer, the slave has to erminate the data transfer or acknowledge pattern with Nst clock cycles(one data cycle and end bit cycle). If the master terminates boot mode between consecutive blocks, the slave must release the data line with Nst clock cycles.
Boot operation will be terminated when all contents of the enabled boot data are sent to the master. After boot operating is executed, the slave shall be ready for CMD1 operation and master need to start a nmormal MMC initialization sequence by sending CMD1.
부트 작업은 활성화된 부트 데이터의 모든 내용이 마스터로 전송되면 종료됩니다.
부트 작업이 실행된 후,
슬레이브는 CMD1 작업을 준비해야 하며,
마스터는 CMD1을 전송하여 정상적인 MMC 초기화 시퀀스를 시작해야 합니다.
Min 8 clocks + 48clocks = 56 clocks required from CMD signal high to next eMMC command. If the CMD line is held LOW for less than 74 clock cycles after power-up before CM1 is issued, or the master sends any normal eMMC command other tan CMD0 with argument 0xFFFFFFFA before initiaing boot mode, the slave shall not repond and shall be locked out of boot mode wuntill the nextpowercycle of hardware reset and shall enther INDLE Sate.
CMD 신호가 HIGH 상태로 전환된 후 다음 eMMC 명령을 전송하기 전에 최소 8 클럭 + 48 클럭 = 총 56 클럭이 필요합니다.
전원이 켜진 후 CMD1이 발행되기 전에 CMD 라인이 74 클럭 사이클 미만으로 LOW 상태로 유지되거나,
부트 모드를 시작하기 전에 마스터가 인수 0xFFFFFFFA와 함께 CMD0 이외의 일반 eMMC 명령을 보내는 경우,
슬레이브는 응답하지 않고 부트 모드에 진입하지 못하도록 잠금 상태가 됩니다.
이후 다음 전원 주기 또는 하드웨어 리셋이 발생할 때까지 이 상태가 유지되며, 슬레이브는 IDLE 상태로 진입합니다.When BOOT_PARTITION_ENABLE bits are set and master send CMD1 (SEND_OP_COND), slave must enter device Identification Mode and respond to the command. If the slave does not support boot operation mode, per v 4.2 or prioir, or BOOT_PARTITION_ENABLE bit is cleared, slave automatically enter IDLE State after power-on.
6.3.4 Alternative boot operation
