CPU설계

full adder

module fa1 (a, b, ci, co, s);
input a, b, ci;
output co, s;
assign co = (a&b) | (ci&a) | (ci&b);
assign s = a^b^ci;
endmodule

Arithmetic

module inp_logic  (s, b, y);
input  b;
input [1:0] s;
output reg y;

always @ (s,b) begin
 case(b)
1:  if(s == 2'b11)begin
	y = 1;
	end
    else if(s == 2'b01)begin
	y = 1;
	end

    else if(s == 2'b10)begin
	y = 0;
	end

	else begin
	y = 0;	
	end 

default:
	 if(s == 2'b11)begin
	y = 1;
	end
    else if(s == 2'b01)begin
	y = 0;
	end

    else if(s == 2'b10)begin
	y = 1;
	end

	else begin
	y = 0;	
	end 
endcase
end
endmodule

module ari_oper16(cin, s, a, b, cout, g);
parameter BW = 16;
input cin;
input [1:0] s;
input [BW-1:0] a, b;
output [1:0] cout;
output [BW-1:0] g;
wire [BW-1:0] y;

wire[BW:0] carry_wire;

assign carry_wire[0] = cin;
assign  cout = carry_wire[BW:BW-1];

generate
	genvar i;
	for (i =0 ; i<=BW-1; i =i+1) begin : gen_roop16
		inp_logic  inp (.s(s), .b(b[i]), .y(y[i]));	
		fa1 fa (.a(a[i]), .b(y[i]), .ci(carry_wire[i]), .co(carry_wire[i+1]), .s(g[i]));
	end

endgenerate

논리 연산화로

비트별 연산
S1 S0 : 4개 연산 선택
4 to 1 MUX

module fa1 (a, b, ci, co, s);
input a, b, ci;
output co, s;
assign co = (a&b) | (ci&a) | (ci&b);
assign s = a^b^ci;
endmodule