High-level Synthesis Flow

• Load design & technolgy data
• Apply timing constraints (current stage)
• Synthesize the design
• Analyze results
• Write out design data

3장에서 clock, input/output delay 등에 대한 제약 조건을 설정했지만 아직 정확한 타이밍 분석을 하기에는 불충분하다.
따라서 4장에서 Driving Cell과 Load Cap과 같은 환경 요소에 대한 제약 조건을 적용해보고자 한다.

Environmental Attributes

Objectives

• Apply environmental attributes to model the timing effects of :
  • Input drivers and transition times
  • Output load cap
• Load budgeting

Input Driving cell & Input Transition times

• By default, DC assumes ZERO transition of input port
  → This would result in optimistic I/O paths timing
  → Optimistic Path Timing reults is bad because we design it with Worst case in mind

• Transition Time & setup Time

  • If $T_{transition} < T_{setup}$,
    → 신호가 setup time동안 안정화될 수 있다고 판단하여 이를 고려하지 않음!
  • If $T_{transition} > T_{setup}$,
    → Transition delay를 고려해야 함!

• Modeling

  • Input Transition
    set_input_transition -max 0.12 [get_ports INB]
  • Driving Cell
    set_driving_cell -max -lib_cell OR3B [get_ports INA]
set_driving_cell -max _lib_cell FD1 -pin Qn [get_ports INA]
    → driving cell의 transition time을 도출하여 Input port에 적용하는 방법
    → 입력 포트가 실제로 지정된 driving cell에 의해 구동될 것으로 예상될 때 사용
    → driving cell의 출력 Pin이 여러개인 경우, 지정해줘야함
  • DRC 무시하는 방법
    set_driving cell -no_design_rule
    → driving cell을 의도적으로 특정 값을 지정하여, constraint를 과소, 과대 적용하여 분석할 때 사용

Output Load cap

• By defaults, DC assumes ZERO load cap of output port
  → This would result in ※optimistic I/O paths timing
  → Optimistic path timing is bad things, cuz we design it with worst case in mind

• Modeling

  • Load cap to value
    set_load -max [expr {30.0/1000}] [get_ports OUTB]
  • Load cap using cell
    set_load -max [load_of lib/cell/pin_name] [get_ports OUTB]
set_load -max [expr {[load_of lib/cell/pin_name]*3} [get_ports OUTB]

Load Budgeting

• Load Budgeting : my_design 외부에 대해 전혀 모를 때, load를 설정하는 것
• Modeling
  • Assume a weak driving cell for worst case analysis
    set_driving_cell -max -no_design_rule -lib_cell inv1a1 $ALL_INPUT
  • Limit the input capacitance of each input port
    set_max_capacitance [expr {[load_of libname/and2a1/A] * 10}] $ALL_INPUT
  • Estimate the number of other major blocks your outputs may have to drive
    set_load -max [expr {expr {[load_of libname/and2a1/A] * 30}] [all_outputs]

Lab

my_design.v → Read → Constraints → Verify → Save → MY_DESIGN.ddc
  (RTL)         (source MY_DESIGN.con)              (unmapped)

• All input ports, except clk & Cin, are driven by bufbd1 buffers
  set ALL_INPUT [remove_from_collectoin [all_inputs] [get_ports {Clk Cin*}]]
set_driving_cell -max -library cb13fs120_tsmc_max -lib_cell bufbd1 $ALL_INTPUT

• Port Cin is a chip level input and has an input transition of 120ps
  set_input_transition 0.12 [get_ports Cin*]

• All outputs, excepts Cout, drive 2x bufbd7 loads
  set_load [expr 2 * {load_of cb13fs120_tsmc_max/bufbd7/I}] [get_ports out*]

• Cout drives 25fF
  set_load 0.025 [get_ports Cout*]

• Operating condition use to scale cell and net delays
  set_operating_conditions -max cb13fs120_tsmc_max

ETC

Find the cell library

get_lib_cells */bufdb1