High-level Synthesis Flow

• Load design & technolgy data
• Apply timing constraints (current stage)
• Synthesize the design
• Analyze results
• Write out design data

7장에서는 다시 "apply timing constraints" 부분으로 돌아와서 추가적인 constraint options에 대해 알아보고자 한다.

Additional Constraint Options

Objectives

• Clock with non-default duty cycle
• Multiple external input/output paths
• External inputs/outpus clocked by negative edge
• Clock Latencies independent of pre-/post-CTS timing analysis

Clock

• Name
• Duty-cycle
• Offset(latency)
• Complex

Data

• Input delay (rise/fall/multi)
• Driving cell(=transition of port)
• Output delay

Pre/Post-CTS

• Pre-CTS : Ideal clock latency
• Post-CTS : Propagated clock sources

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