๐Ÿ’พ ARM ํ”„๋กœ์„ธ์„œ

Dayonยท2023๋…„ 1์›” 28์ผ
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CS๊ณต๋ถ€

๋ชฉ๋ก ๋ณด๊ธฐ
11/18

๐ŸŒฑย ๋“ค์–ด๊ฐ€๊ธฐ

ARM = Advanced RISC Machine = ์ง„๋ณด๋œ RISC์˜ ๊ธฐ๊ธฐ

RISC (Reduced Instruction Set Computer) ํ”„๋กœ์„ธ์„œ๋ž€ ?

  • CISC์—์„œ ๊ฐ„๋žตํ™” ๋œ ์†Œ์ˆ˜์˜ ๋ช…๋ น์–ด๋“ค๋งŒ ์ง€์›ํ•˜๋Š” ์ƒˆ๋กœ์šด CPU ๊ตฌ์กฐ์˜ ๋„์ž…
  • ๊ณ ์ •๋œ ๊ธธ์ด์˜ ๋ช…๋ น์–ด์™€ ์ œํ•œ๋œ ๊ฐœ์ˆ˜์˜ ๋ช…๋ น์–ด๋ฅผ ์ง€์›ํ•ด ๋‹จ์ˆœํ•œ ๋ช…๋ น์–ด๋ฅผ ๋น ๋ฅด๊ฒŒ ์ˆ˜ํ–‰ํ•˜๋Š” ๊ตฌ์กฐ
  • ๋งŽ์€ ์ˆ˜์˜ ๋ ˆ์ง€์Šคํ„ฐ๋ฅผ ์‚ฌ์šฉํ•ด ๋ฉ”๋ชจ๋ฆฌ ์ ‘๊ทผ์„ ์ค„์ด๊ณ , ์ฃผ๊ธฐ์–ต์žฅ์น˜ ์ ‘๊ทผ์„ ์ตœ์†Œํ™”ํ•˜๋Š” ๊ตฌ์กฐ
๊ตฌ๋ถ„RISCCISC
๋ช…๋ น์–ด ํ˜•์‹๊ณ ์ •๊ฐ€๋ณ€
๋ช…๋ น์–ด ์ข…๋ฅ˜์ ์Œ๋งŽ์Œ
๋ช…๋ น์–ด ๊ธธ์ด๊ณ ์ •๊ฐ€๋ณ€
์ ์žฌ/์ €์žฅ ๊ตฌ์กฐ์‚ฌ์šฉ๋ฏธ์‚ฌ์šฉ
์ฃผ์†Œ ์ง€์ • ๋ฐฉ์‹๋‹จ์ˆœํ•˜๊ณ  ์†Œ์ˆ˜๋ณต์žกํ•˜๊ณ  ๋‹ค์ˆ˜
ํšŒ๋กœ ๊ตฌ์„ฑ๋‹จ์ˆœ๋ณต์žก
์žฅ์ ๊ตฌํ˜„์šฉ์ด, ํŒŒ์ดํ”„๋ผ์ด๋‹์— ํšจ์œจ์  ์ ์šฉํ˜ธํ™˜์„ฑ ์–‘ํ˜ธ, ์ฝ”๋“œ ๋ฐ€๋„ ์–‘ํ˜ธ
์˜ˆARM, PowerPC, MIPSIntel x86, DEC VAX 11/780

1983๋…„ Arcon์‚ฌ์—์„œ Berkley RISC-I๋ฅผ ๋ณ€ํ˜•ํ•˜์—ฌ ARM CPU ๊ฐœ๋ฐœ

์„ฑ๋Šฅ ๋ณด๋‹ค๋Š” ์ œ์–ด ๋“ฑ์˜ ์‚ฐ์—…์šฉ ํŠน์„ฑ์— ๋งž๊ฒŒ ์†๋„์™€ ๋น„์šฉ์„ ์ค‘์‹œํ•˜๋Š” ๋ณ€ํ˜•๋œ RISC ๊ตฌ์กฐ (Exception ์ฒ˜๋ฆฌ ๊ฐ•ํ™”, ์†Œํ˜•ํ™”, ์ง‘์ ํ™”, ์ €์ „๋ ฅํ™”์— ์ง‘์ค‘)

ARM์€ Core๋ถ€๋ถ„๋งŒ ๊ฐœ๋ฐœ, ์ƒ์‚ฐ์€ ํ•„์š”๋กœ ํ•˜๋Š” ์—…์ฒด๊ฐ€ ์ž์‹ ๋“ค์ด ํ•„์š”๋กœ ํ•˜๋Š” ์ฃผ๋ณ€์žฅ์น˜ ํšŒ๋กœ๋“ค์„ ๋‚ด์žฅ์‹œ์ผœ 1-chip ํ˜•ํƒœ์˜ ๋งˆ์ดํฌ๋กœ ์ปจํŠธ๋กค๋Ÿฌ๋ฅผ ์ƒ์‚ฐ


๐Ÿซฅ ํŠน์ง•

  • ๋‹จ์ˆœํ™” ์„ค๊ณ„๋ฅผ ํ†ตํ•œ ์ฝ”์–ด ์ตœ์†Œํ™”, ์ €์ „๋ ฅ์šฉ ๊ตฌ์กฐ โ†’ Embedded System์— ์ตœ์ ํ™”

  • ๋‹จ์ˆœ์„ฑ์ด ๊ฐ•์กฐ๋œ ๋ณ€ํ˜•๋œ RISC ๊ตฌ์กฐ

    -๊ฐ€๋ณ€ Cycle ๋ช…๋ น์–ด ์กด์žฌ(๋ฉ”๋ชจ๋ฆฌ ๋ธ”๋ก์ „์†ก), Register Window๋ฅผ ์ค„์ธ Shadow Register์‚ฌ์šฉ ๋“ฑ

  • ํ•˜์œ„ ๋ช…๋ น์–ด ๊ตฌ์กฐ๋ฅผ ์œ ์ง€ํ•˜๋ฉด์„œ ๋ฐœ์ „ (ISA)

  • Pipeline

  • ์ฃผ์†Œ ๊ณต๊ฐ„ (์ฃผ์†Œ 32๋น„ํŠธ, Memory-mapped I/O, ๋‹ค์–‘ํ•œ Addressing ๋ชจ๋“œ)

  • ๋ ˆ์ง€์Šคํ„ฐ ๊ตฌ์„ฑ (๋ฒ”์šฉ ๋ ˆ์ง€์Šคํ„ฐ 30๊ฐœ, PC 1๊ฐœ, CPSR 1๊ฐœ, SPSR 1๊ฐœ, Load-Store ๊ตฌ์กฐ)

  • ํ”„๋กœ์„ธ์„œ ๋‚ด๋ถ€์— ํ•˜๋“œ์›จ์–ด ๋””๋ฒ„๊ทธ ๊ธฐ์ˆ  ํฌํ•จ



ARM ์•„ํ‚คํ…์ฒ˜, ์ฝ”์–ด, ํ”„๋กœ์„ธ์„œ

ARM ์•„ํ‚คํ…์ฒ˜ : ๋ช…๋ น์–ด, ๋ ˆ์ง€์Šคํ„ฐ ๊ตฌ์กฐ, ์ฒ˜๋ฆฌ๋˜๋Š” ๋ฐ์ดํ„ฐ ํฌ๊ธฐ ๋“ฑ๊ณผ ๊ฐ™์€ ๊ธฐ๋ณธ๊ตฌ์„ฑ ๋ฐ ๋™์ž‘ ์›๋ฆฌ

ARM ์ฝ”์–ด : ARM ์•„ํ‚คํ…์ฒ˜์˜ ๊ธฐ๋ณธ์›๋ฆฌ๋ฅผ ์ด์šฉํ•ด ๋งŒ๋“  ํ”„๋กœ์„ธ์„œ ์ฝ”์–ด

ARM ํ”„๋กœ์„ธ์„œ : ARM ์ฝ”์–ด์— ์ฃผ๋ณ€ํšŒ๋กœ๋ฅผ ํฌํ•จํ•˜๋Š” ๋…๋ฆฝ๋œ ํ˜•ํƒœ, ๊ฐ ๋ฐ˜๋„์ฒด ์—…์ฒด๋งˆ๋‹ค ์ƒ์‚ฐํ•˜๋Š” SoC



๐Ÿ†ย ARM ๋ฒ„์ „



โ›‘๏ธย ARM ๋ช…๋ น์–ด ์ฒ˜๋ฆฌ

  • ARM ๋ช…๋ น์–ด ๋ถ„๋ฅ˜

    ์‚ฐ์ˆ  ๋ช…๋ น์–ด, ๋…ผ๋ฆฌ ๋ช…๋ น์–ด, ์‹œํ”„ํŠธ ๋ช…๋ น์–ด, ๋น„๊ต ๋ช…๋ น์–ด, ์ด๋™ ๋ช…๋ น์–ด, Load/Store ๋ช…๋ น์–ด, ๋ถ„๊ธฐ ๋ช…๋ น์–ด

  • ARM ๋ช…๋ น์–ด ์„œ์‹

    ๋ฐ์ดํ„ฐ ์ฒ˜๋ฆฌ ๋ช…๋ น ํ˜•ํƒœ OP-code Rd,Rn,Rx

    Load/Store ๋ช…๋ น ํ˜•ํƒœ (LDR, STR ๋ช…๋ น์–ด) OP-code Rd,[Rn,Rx]

  • ARM ๋ช…๋ น์–ด ์ฒ˜๋ฆฌ ๊ณผ์ •

    FETCH โ†’ DECODE(Reg Select, Reg Read) โ†’ EXECUTE(Shift, ALU์—ฐ์‚ฐ) โ†’ Memory โ†’ Write(Register Write)

  • ARM ๋ชจ๋“œ (32bit) ์ƒ์„ธ ๋ช…๋ น์–ด ํ˜•์‹

    ๋ช…๋ น์–ด 32๋น„ํŠธ ๊ตฌ์„ฑ

    โ†’ Condition(4) + Opcode(8) + Destinaiton(4) + Source1(4) + Source2(12)

    ์กฐ๊ฑด๋ถ€ ์‹คํ–‰์„ ํ†ตํ•ด ๋ถ„๊ธฐ ๋ช…๋ น์„ ๋ฐฐ์ œํ•ด์„œ ํŒŒ์ดํ”„๋ผ์ธ ๊ธฐ๋Šฅ์„ ์ตœ๋Œ€ํ™” ํ•œ๋‹ค

    ~~> ๋ช…๋ น์–ด๊ฐ€ ์ค„๊ณ , CODE ์ถ•์†Œ ํšจ๊ณผ์™€ ํŒŒ์ดํ”„๋ผ์ธ ๊ธฐ๋Šฅ์„ ์ตœ๋Œ€ํ™” ์‹œํ‚ฌ ์ˆ˜ ์žˆ๋‹ค.




๐Ÿ”—ย ์ฐธ์กฐํ•œ ์‚ฌ์ดํŠธ

https://gyoogle.dev/blog/computer-science/computer-architecture/ARM%20%ED%94%84%EB%A1%9C%EC%84%B8%EC%84%9C.html

https://codedosa.com/2110



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