5. Modes of Operation

5-1. Introduction

5-1-1. PL(Privilege Level)

• Privilege level(PL) define authorization that access to system resource(e.g. memory, MMU, cache, interrupt)
• ARM has 4 level(PL0 - PL3): PL3 > PL2 > PL1 > PL0
  • PL0: Unprivileged Level, User mode
    • can't access to MMU, cache, interrupt...
      • can't directly access to memory
  • PL1: SVC, IRQ, FIQ, ABT, UND, STS
    • directly access to memory
      • access to system resource(MMU, cache)

5-1-2. Opeartion Modes

Mode	Function	Level
User(USR)	User application	PL0
Supervisor(SVC)	System call, kernel	PL1
IRQ	IRQ interrupt	PL1
FIQ	FIQ interrupt	PL1
Abort(ABT)	Memory Abort exception	PL1
Undef(UND)	Undefined Instruction exception	PL1
System(SYS)	Share User mode's register view(?)	PL1

5-2. Reigsters

5-2-1. CPSR Register

• When we want to change mode → have to change mode bit in CPSR. CPSR[4:0]
  • PSTATE doens't record mode. it record level in PSTATE[3:2]
• In PL0, we can't access to CPSR. but in PL1, we can.

5-2-2. SPSR Register

• SPSR is copy set of CPSR when we have to change mode.
• We recover processor's state using SPSR's data after handling trap.

5-3. Instruction Change Mode

5-3-1. MSR CPSR_C

MSR CPSR_C, #MODE | I_BIT | F_BIT 

• MSR instruction can't control whole CPSR
  • Mode bits([4:0]) + IRQ Mask([7]) + FIQ Mask([6])
  • bit[5] is Thumb mode. Rarely used.

5-3-2. MOVS, SUBS

• Change mode to saved value in SPSR

SUBS PC, LR, #4
MOVS PC, LR

5-4. Linux Kernel with ARMv7

5-4-1. Stack initialization

MOV		IP, SP
PUSH	{R4, R5, FP, IP, LR, PC}
MSR		CPSR_c, #210				// we are interested from here
ADD		LR, R4, #0
MOV		SP, LR
MSR		CPSR_c, #215
ADD		LR, R4, #12
MOV		SP, LR
MSR		CPSR_c, #219
ADD		LR, R4, #24
MOV		SP, LR
MSR		CPSR_c, #209
ADD		LR, R4, #36
MOV		SP, LR
MSR		CPSR_c, #211
LDM		SP, {R4, R5, FP, SP, PC}

• Sample

MSR		CPSR_c, #210	; 0xd2
ADD		LR, R4, #0
MOV		SP, LR

1. MSR CPSR_c, #210: Set CPSR's [7:0] bits as 0xd2(11010010)
   • IRQ = 1, FIQ = 1, Thumb = 0, mode = IRQ
   • change mode to IRQ
2. ADD LR, R4, #0 + MOV SP, LR: Save target address(stack address) in R14 and move them in to SP(R13 + R13_irq)

• Other line also do same thing like this(IRQ, ABT, UND, FIQ, SVC)

5-4-2. Exception Switch

• Interrupt handling process in ARM
  • when interrupt call, then ARM processor switch to IRQ mode
  • In Irq mode, processor search proper handler using IRQ interrupt exception vector
  • Handler is kernel code. To execute handler, processor change to SVC mode
  • Run interrupt service routine
  • Return to user mode