1. Operands of the Computer Hardware

Word

A natural unit of access in a computer, usually a group od 32bits; corresponds to the size of a register in the RISC-V architecture.

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1. 1. Memory Operands

1) Main memory used for composite data

Programming language have simple variables that contain single data elements, but also have more complex data structures - arrays and structures.

these composite data structures can contain many more data elements than there are registers in a computer.

How can computer represent and access such large structures?

The processor can keep only a small amount of data in registers, but computer memory contains bilions of data elements.

2) To apply arithmatic operations

Arithmatic operations occur only on registers in RISC-V.
산술연산을 할 때에는 오직 레지스터에 저장된 값을 이용하여 연산할 수 있다.

It means, RISC_V must include instructions that transfer data between Memory and Registers.
따라서 메모리의 값을 이용하여 연산하거나, 연산결과를 메모리에 저장하고 싶을 때는 메모리에 접근하는 별도의 연산과정이 필요하다.

Such instructions are called Data Transfer Instructions.
이런 별도의 연산 과정을 Data Transfer Instruction 이라 하고, 이를 Load, Store라고 편히 부르기도 한다.
즉, Data Transfer Instruction에서 메모리 피연산자가 필요하다.

Data Transfer Instructions
: A command that moves data between memory and registers.
Load values from memory into registers. 메모리에 접근하여 데이터를 레지스터에 저장하여 이후에 산술연산 할 수 있게 함.
Store result from register to memory.레지스터에 있는 값을 메모리에 저장함.

3) RISC-V is Little Endian

Little Endian
Least-significant byte at least adress of a word.
낮은 주소에, 데이터의 낮은 바이트부터 저장하는 바이트 저장 방식. 인텔 CPU계열에서 이 방식으로 데이터를 저장한다.

RISC-V Memory Addresses

1) Memory is byte addressed

Each address identifies an 8-bit.
Since 8-bit (1 byte) are useful in many programs, most architectures address individual byte.
Therefore, the address of a word matches the address of one of the 4 bytes within the word, and addresses of sequential word differ by 4.

기본적으로 byte 단위로 접근하게 된다. 또한 4byte가 하나의 word를 구성한다.

2) NO Alignment Restriction

A requirement that data be aligned in memory on natural boundaries.

In many architectures, words must start at addresses that are multiples of 4.
RISC-V and Intel x86 do not have alignment restrictions, but MIPS does.

EX) Compiling an Assignment When an Operand is in Memory

• A : array of 100 words
• variables g and h with the registers x20, x21
• Base address* : x22
• off set** : 8

process 1)

Although there is a single operation in this assignment statement, one of the operands is in memory.
So, we must transfer A[8] to a register.

lw	x9, 32(x22)

The address of what we need is the sum of the base of the array A, which found in register x22, plus the number to selec element 32.

Off Set & Base Address
상대주소 Offset : Base address로부터의 변위차를 byte 단위로 나타낸다.
Base Address : Offset의 기준이 되는 주소.

process 2)

add	x20, x21, x9

since it is in a register. The instruction must add h (contained in x21) to A[8] (contained in x9) and put the sum in the register corresponding to g (associated with x20)

process 3)

sw	x9, 48(x22)

The final instruction stores the sum into A[12], using 48 (4 × 12)byte as the offset and register x22 as the base register