Instruction and Data Cache

• We can keep the data and instructions in the same cache – unified cache

• When a load/store instruction is executed, the processor will simultaneously request both data and instruction, cause structural hazard.

• We can keep them in separate caches – split cache: instruction cache and data cache. We can also optimize each cache separately

AMAT = Hit_Time + Miss_Rate * Miss_Penalty

Problem 1

Which has the lower miss rate: a 16KB instruction cache with a 16KB data cache or a unified 32KB cache? Use the following data for number of misses per 1000 instructions:

32KB  
instruction_cache:1.36 
data_cache:38.4 
unified_cache:43.4

16KB 
instruction_cache:3.82
data_cache:40.9
unified_cache:51

Assume 36% of instructions are data transfer instructions, a hit takes 1 clock cycle and penalty is 200 clock cycles. A load or store takes 1 extra clock cycle on a unified cache if there is only one port. What is the overall miss rate for the split caches, what is the average memory access time for both cases?

We are comparing:

$\boxed{\text{Split: 16KB I-cache + 16KB D-cache}}$
versus
$\boxed{\text{Unified: one 32KB cache}}$

Both have the same total capacity, 32 KB.

Problem 2

What is the impact of two different cache organizations on the performance of a CPU?

Assume that CPI for a perfect cache is 1.6, clock cycle time is 0.35ns, there are 1.4 memory references per instruction, size of both caches is 128KB and block size is 64B.

One cache is direct mapped and the other is 2-way set associative. For a set associative cache assume that clock cycle is 1.35 times. Cache miss penalty is 65ns for both caches.

Calculate memory access time and then CPUtime. Assume that hit time is 1 clock cycle, the miss rate of direct mapped cache is 2.1% and the miss rate of set associative cache is 1.9%.