Computer Arch (Memory)

Response time (also called executiontime) \- How long it takes to do a taskThroughput \- Total work done per unit time \- e.g., tasks/transaction

Each task is called pipe stage or pipe segmentStage duration is called the processor cycleAll stages must be able to proceed at the same time: – It is

We would like to have a lot of fast memory, but smaller memory units are fasterFrequently application accesses to data exhibit spatial andtemporal loc

Consider two different implementations of the same instruction set architecture. The instructions can be divided into four classes according to their

Q1: Where can a block be placed in the upper level?(Block placement)Q2: How is a block found if it is in the upper level?(Block identification)Q3: Whi

64-bit address, 2-way set associative, cache size 128KB (only for the data part), block size 16BSet-IndexTag ComparisonData TransferRead Hit time: 1 +

Memory Reference는 CPU가 메모리 계층(Cache / Memory)에 한 번 접근하는 것을 의미한다. 주로 두 종류가 있다.A memory reference means one access to the memory hierarchy/cache.In thes

Which has the lower miss rate: a 16KB instruction cache with a 16KB data cache or a unified 32KB cache? Use the following data for number of misses pe

Compulsory – first time when we want to access a block, cold-start misses.Capacity – if cache cannot hold all blocks needed in a programConflict – if

Reducing Miss Penalty Multi-Level Caches Victim Caches Multi-level Caches There is a trade-off between the size of the cache and the access time Sm

Assume we are using 32-bit address. L1 cache is direct mapped and size is 16KB, block size is 32B. L2 cache is 8-way set associative and size is 4MB,

The main idea is that L1 and L2 have different jobs, so they are intentionally designed differently.differently.$\\boxed{\\text{L1: optimize for speed

2. Victim Caches Victim cache holds data that has been deleted from the cache, in case it is needed again This is fully associative cache and can help to reduce misses with direct-mapped or set assoc...

Hit time is the time to find data that is in the cache: use the index to pick a set, read its tag(s) and data, compare tags, then choose the right blo

A processor's clock cycle can be no shorter than its slowest single step (the critical path). A cache access is one of the slowest steps: decode the i

You are building a computer system around a processor with in-order execution that runs at 1 GHz and has a CPI of 1, excluding memory accesses. The on