Block: 1 cache line stores 1 block
Cache line = one cell
Block = the data stored inside that cell
Block size = how many bytes that cell stores

1.

Assume we are using 32-bit address. L1 cache is direct mapped and size is 16KB, block size is 32B. L2 cache is 8-way set associative and size is 4MB, block size is 64B. Draw the cache access diagram for L1 and L2 cache respectively, and indicate the size of all fields (in bits) and the size of L1 and L2 caches (in number of blocks they can hold). You may use the Lec5-slide8 as a reference.

2.

You have split caches (a 32KB instruction cache and a 32KB data cache) with the following specifications:

• Hit time is 1 clock cycle and miss penalty is 100 cycles
• There are 38.4 misses per 1000 instructions for 32KB data cache, and 1.36 misses per 1000 instructions for 32KB instruction cache.

Assume 40% of instructions are data transfer instructions, CPI is 1 when all memory accesses hit in the cache.

(a) What is the overall average memory access time for the split caches?

(b) What is the overall average memory stalls per instruction for the split caches?

(c) What is the overall CPUtime (expressed as function of IC - instruction count)?

3.

You have a two-level cache with the following specifications:

• L1 is 64KB direct-mapped with 32B blocks. Hit time is 1ns and local miss rate L1 is 5%
• L2 is 1MB 4-way set-associative with 128B blocks. Hit time is 20ns and global miss rateL2 is 2%
• Penalty to fetch block from memory to L2 is 60ns

What is the average memory access time?