Sample Cache Access Diagram

• 64-bit address, 2-way set associative, cache size 128KB (only for the data part), block size 16B

hit time

1. Set-Index
2. Tag Comparison
3. Data Transfer

Read Hit time: 1 + MAX(2,3) + MUX
Write Hit time: 1 + 2 + 3
-> Write takes longer than reads

Q3: Which block should be replaced on a miss?

Easy for Direct Mapped
Set Associative or Fully Associative:

• Random: Easy to implement, how well does it work?
• LRU (Least Recently Used): Appealing,but hard to implement for high associativity

Q4: What happens on a write?

Write takes longer than reads: read can start in parallel with tag checking, but write cannot.

Instruction and Data Cache

• We can keep the data and instructions in the same cache – unified cache

• When a load/store instruction is executed, the processor will simultaneously request both data and instruction, cause structural hazard.

• We can keep them in separate caches – split cache: instruction cache and data cache. We can also optimize each cache separately.