the ARM Cortex-M3 Processor - 1

2.9.1 Low Power and High Energy Efficiency

The Coretx-M3 is desigmed with various features to allow designers to develop low power and high energy efficient products. First, it has sleep mode and deep sleep mode supports, which can work with carious system design methodologies to reduce power consumption during idle period.

Exception Number	Exception Type	Prioirty(Default to 0 if Programmable )	Description
0	NA	NA	No exception running
1	Reset	-3	Reset
2	NMI	-2	NMI(external NMI input)
3	Hard Fault	-1	All fault conditions, if the corresponding fault handler is not enabled
4	MemManage fault	Prgrammable	Memory management Fault;MPU violation or access to ilegal locations
5	Bus fault	Programmable	Bus error(prefetch abort or data abort)
6	Usage Fault	Programmable	Program error
7~10	Revsered	NA	Reserved
11	SVCall	Prgramable	Supervisor call
12	Debug monitor	Program	Debug monitor(break points, watchpoints, or external debug request
13	Reserved	NA	Reserved
14	PendSV	Prgram	Renalbe request for system servie
15	SYSTICK	Prgram	System tick timer

Second, its low gate count and design techniques reduce circuit activities in the processor to allow active power to be reduced.

In addition, since Cortex-M3 has high code density, it has lowered the program size requirement. At the same time, it allows processing tasks to be completed in a short time, so that the processor can return to sleep modes as soon as possible to cut down energy use. As a result, the energy efficiency of Cortex-M3 revision 2, a new feature called Wakeup Interrupt Controller(WIC) is acailable. This feature allows the whole processor core to be powered down, while processosor states are retained and the processor can be returned to active state alomost immediately when an interrupt takes place. This makes the Cortex-M3 even more suitable for many ultra-low power applications that previously could only be implemeted with 8 bit 16 bit microcontroller.

전체적으로, 높은 코드 밀도, 효율적인 처리 및 Wakeup Interrupt Controller(WIC)와 같은 저전력 기능의 조합은 Cortex-M3를 성능과 저전력 소비를 모두 요구하는 다양한 임베디드 애플리케이션에 대한 강력하고 에너지 효율적인 선택지로 만들어 줍니다.

2.10 DEBUGGING SUPPORT

The Cortex-M3 Processor includes a number of debugging features, such as program execution controls, including halting and stepping, instruction breakpoints, data watchpoints, registers and memory accesses, profilin, and traces

The debugging hardware of the Cortex-M3 is based on the CoreSight architecture. Unlike traditional ARM processors, the CPU core itself does not have a JTAG interface. Instead, a debug interface module is decoupled from the core , and bus interface called the Debug Access Port(DAP) is provided at the core level. Throught this bus interface, external debuggers can access control registers to debug hardware as well as system memory, even when the processor is runnung. The control of this bus interface is carried out by a Debug Port Devices. Th DPs currently available are the Serial Wire JTAG Debug Port(SWJ-DP)(suppots the traditional JTAG protocol as well as the Serial Wire Protocol) or the SW-DP(supports the Serial-Wire protocol only_. A JTAG DP module from the ARM CoreSight product family can also be used. Chip manucfacturers can choose to attach one of these DP modules to provide the debug interface.

Chip manufacturerers can also include an Embedded Trace Macrocell to allow instruction trace. Trace information is output via the Trace Port Interface Unit, and the debug host(usually PC) can then collect the executed instruction information via external trace capturing hardware.

칩 제조업체는 Embedded Trace Macrocell (ETM)을 포함하여 명령어 트레이스를 가능하게 할 수 있습니다. 트레이스 정보는 Trace Port Interface Unit (TPIU)를 통해 출력되며, 디버그 호스트(일반적으로 개인용 컴퓨터 [PC])는 외부 트레이스 캡처 하드웨어를 통해 실행된 명령어 정보를 수집할 수 있습니다.

Within the Coretex-M3, a number of events can be used to trigger debug actions. Debug events can be breakpoints, watchpoints, fault conditions, or external debugging request input signals.

When a debug event takes place, the Cortex-M3 processor can either enter halt mode or execute the debug monitor exception handler.

The data watchpoint function is provided by a Data Watchpoint and Trace unit in the Cortex-M3 processor . This can be used to stop the processor(or trigger the debug monitor exception routine) or to generate data trace information. When data trace is used, the traced data can be output via the TPIU. ( In the CoreSight architecture, multiple trace devices can share one sigle trace port.)

In addition to these bsic debugging features, the Cortex-M3 processor also providea Flash Patch and Breakpoint (FPB) unit that can provide a simple breakpoint function or remap an instruction access fro mFlash to a different location in SRAM.

Cortex-M3에서는 여러 이벤트를 사용하여 디버그 동작을 트리거할 수 있습니다. 디버그 이벤트는 중단점(breakpoint), 워치포인트(watchpoint), 오류 조건 또는 외부 디버깅 요청 입력 신호일 수 있습니다.

디버그 이벤트가 발생하면 Cortex-M3 프로세서는 중단 모드로 진입하거나 디버그 모니터 예외 처리기를 실행할 수 있습니다.

An Instrumemtaion Trace Macrocell provides a new way for developers to output data to a debugger. By writing data t oregister memory in the ITM, a debugger can collect the data via a trace interface and isplay or process them. This method is easy to use and faster than JTAG output.

All these debugging components are controlled via the DPA interface bus on the Cortex-M3 or by a program running on the processor core, and all trace information is accessible from the TPIU.

2.11 CHARACTERISTICS SUMMARY

Why is the Cortex-M3 processor such a revolutionary product? What are the advantages of using the Cortex-M3? The nebefus and advantages are summarized in this section.

2.11.1 High Performance
The Cortex-M3 Processor delivers high performance in microcontroller products:

• Mnay instructions, including multiply, are single cycle. Therefore, the Cortex-M3 processor outpoerforms most microcontroller products.

• Separate data and instruction buses allow simultaneous data and instruction accesses to be performed.

• the Thumb-2 instruction set makes state switching overhead history. There's no need to spend time switching between the ARM state(32bits) and the Thumb state(16bites), so instruction cycles and program size are reduced.

• The Thumb-2 instruction set provides extra flexibility in programming. Many data operations can now be simplified using shorter code. This also means that the Cortex-M3 has higher code density and reduced memory requirements.

• Instruction fetches are 32 bits. Up to two instructions can be fetched in one cycle. As a result, there's more available bandwidth for data transfer.

• The Cortex M3 design allows microcontroller products to opertate at high clock frequency(over 100 Mhz in modern semiconductor manufacturing processes). it has a beter clock per ionstrion ratio. This allows more work per MHz or designs can run at lower clock frequency for lower power consumption.

2.11.2 Advanced interrupt handling features

The interrupt features on the Cortex processor are easy to use, very flexible, and provide high interrupt processing throuput:

• The built in NVIC supports up to 240 external interrupt inputs. The vectored interrupt feature considerably reduces interrupt latency because there is no need to used software to determin which IRQ handler to serve. In addition, there is no need to have software code to set up nested interrupt support.

• The processor automatically pushed registers R0-R3, R12, LR, PSR and PC in the stac ka t interrupt entry and pops them back at interrupt exit. This reduces the IRQ handling latency and allow interrupt handlers to be norman C function

• Interrupt arrangement is extremely flexible because the NVIC has programmable interrupt prioirty control for each interrupt. A minimum of eight levels of priority are supported and the priority can be changed dynamically.

• Interrupt latency is reduced by special optimization, including late arrival interrupt acceptance and tail-chain interrupt entry.

• Some of the multicycle operations, including Load-Multiple(LDM), Store-Multiple(STM), PUSH, and POP, are now interruptible.

• On receipt of an NMI requrest, immediate execution of the NMI is very important for many safety-critical applications.

2.11.3 LOW POWER CONSUMPTION
The Cortex processor is suitable for variou low power applications

• The Cortex processor is suitable for low power desings because of the low gate count.

• It has power-saving mode support(SLEEPING and SLEEPDEEP). The processor can enter sleep mode using WFI or WFE instruction. The design has separated clocks for essential blocks, so clocking circuits for most parts of the processor can be stopped dring sleep.

• The fully static, synchronous, synthesizable design makes the processor easy to be manufactured using any low power or standard semiconductor process technology.

2.11.4 System Features

The Cortex-M3 processor provides various system feature making it suitable for a large number of applications :

• The system provides bit band operation, byte-invarinat big endian mode, and unaligned data access support.
• Advanced fault handling features include various exception types and fault status registers, making it easier to locate problems.

With the shadowed stack pointer, stack memory of kernel and user processes can be isolated. With the optional MPU, the processor is more than sufficient to develop robust software and reliable products.

2.11.5 Debug Suppots

The Cortex-M3 processor includes comprehensive debug features to help software develops design their products :

• Supports JTAG or Serial Wire debug interfaces
• Based on the Core Sight debugging solution, processor status or memory contents can be accessed even when the core is running.
• Built in support for six breakpoiints and four watchpoints
• Optional ETM for instruction trace and data trace using DWT
• New debugging features, including fault status registers, new fault exceptions, and Flash Patch operations, make debugging much easier
• ITM provides an easy to use method to output debug information from test code
• PC sampler and counters inside the DWT provide code- profiling information.