Data Setup

1) data setup 끝나고 완성형 디렉토리 구조?

PI에서 오는 파일

• Logic/timing Library Files
  io pad .db
  macro .db
  sd .db

=> .synopsys_dc.setup 에서 set*_library 로 링크
위치 : ./libs/*/LM

• Constraints File : orca.sdc

• Gate-Level Netlist : orca.v

read_verilog ./netlist/<orca.v>
current_design <ORCA>
uniquify
save_mw_cel -as <ORCA>

PD에서 쓰는 파일

• Physical Library Directories
  sc.mw
  io pad.mw
  macro .mw

=> .data_setup.tcl 에서 create_mw_lib <폴더 이름> 으로 technology file, mw 파일 하나로 링크(?)
위치 : ./libs

• Technology File
  <abc_6m>.tf -> 위에 mw_lib에 연결

• TLU+ File : data_setup.tcl 에 작성

파일 세팅 끝나면

P/G 연결, Timing(sdc 파일) 연결

다 끝나면 저장

• tim_opt_ctrl.tcl
  icc_shell 실행하고,
  mw_lib, mw_cel 불러오고 : open_mw_lib <design_lib_orca> open_mw_cel <ORCA_data_setup>
source 로 적용

tcl및 setup

.synopsys_dc.setup

lappend search_path [glob <./libs/*/LM>]

set_app_var target_library "<sc_max/db>"
set_app_var link_library "<*> <sc_max.db> <io_max.db> <macros_max.db>"

set_min_library <sc_max.db> -min_version <sc_min.db>
set_min_library <io_max.db> -min_version <io_min.db>
set_min_library <macros_max.db> -min_version <macros_min.db>

set_app_var symbol_library "<sc.sdb> <io.sdb> <macros.sdb>"

tim_opt_ctrl.tcl

set_app_var timing_enable_multiple_clocks_per_reg true
set_app_var case_analysis_with_logic_constants true
set_fix_multiple_port_nets -all -buffer_constants
set_auto_disable_drc_nets -constant false
set_dont_use <off_limit_cells>
set_prefer -min <hold_fixing_cells>
set_app_var physopt_delete_unloaded_cells false
set_ideal_network [all_fanout -flat -clock_tree]
set_cost_priority {max_transition max_delay}
set_app_var enable_recovery_removal_arcs true
set_max_area 0
set_app_var physopt_power_critical_range <t>
set_app_var physopt_area_critical_range <t>

group_path -name INPUTS -from [all_inputs]

data_setup.tcl

create_mw_lib <design_lib_orca> -open -technology <./libs/abc_6m.tf> -mw_reference_library "<./libs/sc> <./libs/macros> <./libs/io>"

import_designs ./netlist/<orca.v> -format verilog -top ORCA;

set_tlu_plus_files -max_tluplus <./libs/abc_max.tlup> -min_tluplus <./libs/abc_min.tlup> -tech2itf_map <./libs/abc.map>

set_check_library_options -all
check_library
check_tlu_plus_files
list_libs

derive_pg_connection -power_net PWR -power_pin VDD -ground_net GND -ground_pins VSS
derive_pg_connection -power_net PWR -ground_net GND -tie

check_mv_design -power_nets

read_sdc <./cons/orca.sdc>

check_timing

report_timing_requirements
report_disable_timing
report_case_analysis
report_clock
report_clock -skew

source tim_opt_ctrl.tcl

set_zero_interconnect_delay_mode true
report_constraint -all
report_timing
set_zero_interconnect_delay_mode false

remove_ideal_network [get_ports "<Enable Select Reset>"] => <> 부분 일반적인거? 항상 data setup 마지막에 실행해야하나?

save_mw_cel -as <ORCA_data_setup>