Planning

Floorplan 불러오기 : def 파일

read_def <DESIGN.def>

open_mw_lib <my_design_lib>
open_mw_cel <DESIGN_floorplanned>

매번 디자인 열때마다 source tim_opt_ctrl.tcl 적용

placement option 적용

place_opt

CTS 적용

clock_opt

routing option 적용

route_opt

다 끝나고 확인

report_qor
report_constraint -all_violators
report_timing
report_design -physical
report_congestion

각 과정마다 저장하기 -> tcl 로 작성

ex) run.tcl

open_mw_lib design_lib_orca
open_mw_cel ORCA_data_setup
read_def ORCA.def
save_mw_cel -as ORCA_floorplanned

place_opt
save_mw_cel -as ORCA_placed
report_constraint -all

remove_clock_uncertainty [all_clocks]
clock_opt
save_mw_cel -as ORCA_cts
report_constraint -all

route_opt
save_mw_cel -as ORCA_routed
report_consytraint -all
report_timing

close_mw_lib
exit

Floor Planning

1. Core 만들고
   vdd, vss, Corner Cell 만들기

create_cell {vss_l vss_r vss_t vss_b} pv0i
create_cell {vdd_l vdd_r vdd_t vdd_b} pvdi
create_cell {CornLL CornLR CornTR CornTL} pfrelr

2. pad cell 주변에 붙이고

set_pad_physical_constraints -pad_name <name> -side <#> -order <#>

3. 안정성을 위해 corner cell 적용

4. 빈 공간에 filler cell 채움

insert_pad_filler -cell "<fill5000> <> <> "

5. filler cell 넘어가는 P/G ring 생성

derive_pg_connection -power_net VDD -power_pin VSS -ground_net VSS -ground_pin VSS
derive_pg_connection -power_net VDDO -power_pin VSSO -ground_net VSSO -ground_pin VSSO
derive_pg_connection -power_net VDDQ -power_pin VDDQ -ground_net VSSQ -ground_pin VSSQ
derive_pg_connection -power_net PWR -power_pin GND -tie
create_pad_rings

6. P&R 할 때 (메탈의)범위 지정

set_ignored_layers -max_routing_layer <M7>

7. Macro cell constrain 지정
   7-1. IP cell blockage 지정 : Apply Global Placement Blockages, Specific Placement Blockages

set_app_var physopt_hard_keepout_distance <10>
set_app_var placer_soft_keepout_channel_width <25>

set_keepout_margin -type hard -outer {10 0 10 0} RAM5

8. Standard Cell Placement Constraints 지정

이 모든 것을 set_fp_placement_strategy로 지정

set_fp_placement_strategy
    -macro_orientation <automatic | all | N>
    -auto_grouping <none | user_only | low | high>
    -macro_setup_only <on | off>
    -macros_on_edge <on | off>
    -silver_size <0.00>
    -snap_macros_to_user_grid <on | off>
    -fix_macros <none | soft_macros_only | all>
    -congestion_effort <low | medium | high>
    -adjust_shapes <on | off>
    -IO_net_weight <1.0>
    -plan_group_interface_net_weight <1.0>
    -legalizer_effort <low | high>
    -spread_spare_cells <on | off>
    -legalizer_effort <low | high>
    -vertual_IPO <on | off>

끝나면 저장
set_dont_touch_placement [all_macro_cells]
save_mw_cell -as <DESIGN_pre_pns>

Power Planning

1. Logical P/G 지정
2. Macros 주변 P/G Rings 신경쓰기 => 무엇을?
3. Power Network Constraints 지정
4. PNS(Power Network Synthesis) 실행

• Place 과정에서 알아야 할 개념 or 주의점

VIPO : 툴이 timing error가 net가 길어서인지, fanout 때문인지 모르는데 vipo 옵션을 켜줘서 fanout 자동으로 buffer 넣게 만듦
Hierarhical gravity : 기능 별로 cell들을 가깝게 배치
Congestion 신경쓰기
`report_congestion -grc_vased -by_layer -routing_stage global

필요한 부분들 def 파일로 저장