Design Compiler Command

Synopsys verilog directive

• full_case : Specifies that a case statement is to be treated as full case
• parallel_case : Specifies that a case statement is to be treated as parallel case
• infer_mux : Directs synthesis to generate a more robust multiplexer solution
• sync_set_reset : Directs the synthesis tool to check the signals in the list ot determine if they synchronously set or reset the design
• async_set_reset : Directs the synthesis tool to check the signals in the list to determine if they asynchronously set or reset the design
• one_hot : Specifies that the set and reset signals will not be in their active 1'b1 state at the same time
• one_cold : Specifies that the set and reset signals will not be in their active 1'b0 state at the same time
• translate_off / translate_on : Directs the synthesis tool to not synthesize the Verilog code that is in between these two delimiters
• resource : Alerts synthesis that directives to follow are resource block related
• ops : Lists identifiers to be used as labels
• map_to_module : Specifies the DesignWare synthetic part that the operator is to be mapped onto
• implementation : Specifies the archetecture implementation for the selected DesignWare synthetic part
• label : Identifies the operator that is to be synthesized into the specified implementation

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Design Compiler Commands

• set compile_seqmap_synchronous_extraction : Directs synthesis to implement a more robust algorithm when synthesizing flip-flops with synchronous set/reset pins
• set hdlin_ff_always_sync_set_rest : When set to true synthesis is directed to automatically check the coding style for synchronous set and reset conditions of flip-flops
• set hdlin_ff_always_async_set_reset : When set to true synthesis is directed to automatically check the coding style for asynchronous set and reset conditions of flip-flops
• set hdlin_use_carry_in : Directs synthesis to use the carry-in pin of an adder resource block
• set hdlin_infer_function_local_latches : When set to true latches will be synthesized for laatch coding styles in subprograms
• set view_command_log_file : Specifies location of intermediate log files
• set command_log_file : Specifies location of intermediate log files
• set_dont_use : Directs the synthesis tool to not select the specified cells from the target library
• set_test_hold : Specifies value that an input pin should have during the check_test command
• hdlin_enable_presto : Enables/disables Presto Verilog
• hdlin_while_loop_iterations : Specifies the maximum number of times that a Verilog loop statement will be iterated during teh Elaborate phase

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• alias : Renames a synthesis command
• set company : Sets company name toe be displayedin generated schematics
• set designer : Sets designer's name toe be displayed in generated schematics
• set target_library : Specifies a technology or a list of technology libraries from which the synthesis tool will select cells during its mapping to gates stage
• set link_library : Specifies a list of design files and libraries used during the linking phase of a design
• set symbol_library : Specifies the library containing the graphical elements that will be used to generate the schematic output of synthesis

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• define_design_lib Identifies the subdirectory into which the Verilog analyzed files will be seaved
• remove_design -designs : Deletes designs from Design Vision's memory
• compare_design : Checks the functional equivalency of two designs
• check_test : Checks if a design satisfies the observability and controllability rules for test insertion

• read_file -format verilog {<file_name>.v}
• read_verilog <file_name>.v : verilog file 읽기
• analyze -format verilog {<file_name>.v}
• elaborate <design_name>
• read_ddc {<ddc_file_name>.ddc}

• current_design <design_name> : (arg 없으면)현재 디자인 확인 / <design_name>으로 변경
• source <constrain_file_name>.con : constrain file 적용

• check_timing
• link
• compile_ultra

• create_schematic : Creates schematic with default drawing parameters

• create_schematic -no_bus : Creates schematic in which individual lines of bussed signals are isolated

• query_objects : 정보 보기

• filter_collection [get_cells *] "ref_name =~ AN*" : 해당 조건에 만족하는 것들만

• get_cells * -filter "dont_touch == true : 해당 조건에 만족하는 것들만

• list_attributes -application -class <object_type> : attribute 확인

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get_*

• get_nets : current design의 net들. -hier로 sub-block도 가능
• get_pins <cell/pin> : cell들의 input/output pins. -hier로 sub-block 가능
• get_ports : current design의 input/output/bidir ports. -hier 가능
• get_cells : cells(instances) in the current design. -hier 로 sub-blocks도 가능
• get_clocks : current design이나 above design에서 정의된 clock object
• get_designs : DC memory에 있는 designs
• get_libs : DC memory에 있는 libraries
• get_lib_cells <libname/cellname> : library 안에 있는 cell들
• get_lib_pins <libname/cellname/pinname> : library 안에 있는 cell의 pin들

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all_*

• all_inputs : current design의 모든 input, inout ports
• all_outputs : current design의 모든 output, inout ports
• all_clocks : current design과 below에서 정의된 clock들
• all_registers : 현재 디자인의 register cell들의 hierarchy
• all_ideal_nets
• all_fanin
• all_fanout
• all_connected
• all_dont_touch
• all_high_fanout

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*_collection

• add_to_collection : Add object(s)
• compare_collections : compares two collections
• copy_collection : Make a copy of collection
• filter_collection : Filter a collection, resulting in a new collection
• foreach_in_collection : Iterate over a collection
• index_collection : Extract object from collection
• remove_from_collection : Remove object(s) from a collection
• sizeof_collection : Number of objects in a collection
• sort_collection : Create a sorted copy of a collection

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Timing 관련

• create_clock -period <T> -name <virtual_clock_name> : virtual clock 생성
• create_clock -period <T> [get_ports <clock_name>] : clock object 로 바꿔줌, T는 주기
• set_clock_uncertainty -setup <T> [get_clocks <clock_name>] : T = skew + jitter + margin
• set_clock_latency -source -max <source_latency> [get_clocks <clock_name>] : Source Latency 설정
• set_clock_latency -max <network_latency> [get_clocks <clock_name>] : Network Latency 설정
• set_clock_transition -max <T> [get_clocks <clock_name>] : trasition time 설정
• set_propagated_clock [get_ports <clock_name>] : CTS 후에

• set_input_delay -max <T> -clock <clock_name> [get_ports <port_name>] : input port delay
• set_output_delay -max <T> -clock <clock_name> [get_ports <port_name>] : output port delay

활용

• set_input_delay -max 0.5 -clock Clk [remove_from_collection [all_inputs] [get_ports Clk]]

• 다른 옵션 줄 때

  set_input_delay -max 0.5 -clock Clk [all_inputs]
   set_input_delay -max 0.8 -clock Clk [get_ports C]
   remove_input_delay [get_ports Clk]

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Load 관련

input port

1. set_input_transition -max <transition_time> [get_ports <port_name>]
2. set_driving_cell -max -lib_cell <cell_name> -library(not required) -pin(if required) [get_ports <port_name>]

output port

1. set_load -max [load_of <lib_name/cell_name/pin_name>] [get_ports <port_name>]
2. set_load -max <load_value> [get_ports <port_name>]

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report_*

• report_port -verbose : Input, Output delay 확인 가능
• report_clock : period, waveform, source 확인
• report_clock -skew : network delay, transition 확인 가능
• report_clock -skew -attr : 둘 다

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Design Vision Commands

• tools => Setup : Displays current synthesis environment
• File => Analyze : Analyzes specified file
• File => Elaborate : Elaborates specified design
• Tools => Design Optimization : Maps elaborated design onto cells from the target library
• Report => Constraint Analysis => Timing Path : Generates Timing report
• Report => Constraint Analysis => Area : Generates Area Report
• File => Save As : Saves design in specified subdirectory as a .db file
• File => Read : Brings RTL source code and netlists into Design Vision
• View => Preferences => pin_name_layer : Directs schematic output to include pin names of cells selected from target library
• Reports => Design Information => Resources : Generates a resource implementation report

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용어 정리

• supported : 합성 툴이 합성 가능, warning message 뜰 수도 있음
• unsupported : 합성 툴이 합성 못함, error message 발생
• not supported :
• ignored : 합성 툴이 합성 안함, warning message 발생

• Syntehsis = Translation + Optimization + Mapping
• Translate : Presto Verilog Compiler가 수행
  Verilog Hardware Description Language → Generic Boolean(GTECH)
• OPtimize + Map : Design Compiler가 수행
  GTECH → Target Technology

• analyze : Verilog source code를 intermediate format으로 바꾸고 synthesis 에러나 verilog syntax 검사함
  analyze -library <library_name> -format verilog {<file_name>.v}
• elaborate : High-level architectural optimizations(최적화?), syntehsis 에러 검사
  elaborate <design_name> -library <library_name>
• read : analyze + elaborate. library 지정 못함, parameter 값 지정 못함
  read_file -format verilog {<file_name>.v}
• compile : logic level optimizations, maps to gates, gate-level optimization

• Design Vision : Presto Verilog Compiler + Design Compiler
• DesignWare : Technology-independent "soft macros" which are synthesized into gates from your target library

• synthetic_library : DesignWare Library ← Adders, Multipliers, Comparators... 등의 Synthesizable Blocks이 있음
• link_library, target_library : Technology Library ← AND Gates, OR Gates, Flip-Flops... 등의 Primitive Cells이 있음

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Hardware Options

1. 합성하면 NAND gates가 선택된다.

• Gate availabilities in targeted technology
• Circuit speed requirements
• Area minimization requirements

2. buffer가 추가될 수 있다.

• higher drive strength를 위해