Latch와 Flip-Flop

Latch

• Latches 발생 조건
  • Assignment to the variable occurs in at least one, but not all of the branches of a Verilog control statement
  • Assignment to the variable does not occur on a clock's edge

always @ (posedge Clock)
begin

  if (Enable)
    begin
      Data_Out <= In_A;
    end
end

FF으로 합성됨.

always @(Enable, In_A, In_B)
begin

  if (Enable)
    begin
      Out_1 = In_A;
    end
  else
    begin
      Out_2 = In_B;
    end
end

Latch 2개 합성됨

always @(Enable, In_A, In_B, In_E, In_F)
begin

  if (Enable)
    begin
      Out_1 = In_A;
      Out_2 = In_E;
    end
  else
    begin
      Out_2 = In_B;
      Out_1 = In_F;
    end
end

mux 2개로 합성됨. or And gate로 합성될 수도 있음

always @(A, B, Use_B)
begin
  if (Use_B)
    begin
      D_Out = B;
    end
  else if (!Use_B)
    begin
      D_Out = A;
    end
  else
    begin
    D_Out = 1'bz; // For simulation
    $display("Use_B has unexpected value");
    end
end

always @(A, B, Use_B)
begin
  if (Use_B)
    begin
      D_Out = B;
    end
  else
    begin
      D_Out = A;
    end
end

Synthesis tool이 Use_B의 조건을 확인하고 위의 코드를 아래 코드로 줄인다.

case statement latch

input [0:3] Data_In;
always @(Data_In)
begin
  case (Data_In)
    0             : Out_1 = 1'b1;
    1, 3          : Out_2 = 1'b1;
    2, 4, 5, 6, 7 : Out_3 = 1'b1;
    default       : Out_4 = 1'b1;
  endcase
end

이 case statement는 full이면서 parallel하다.
Latch 발생

input [0:3] Data_In;
always @(Data_In)
begin

  Out_1 = 1'b0;
  Out_2 = 1'b0;
  Out_3 = 1'b0;
  Out_4 = 1'b0;
  
  case (Data_In)
    0             : Out_1 = 1'b1;
    1, 3          : Out_2 = 1'b1;
    2, 4, 5, 6, 7 : Out_3 = 1'b1;
    default       : Out_4 = 1'b1;
  endcase
  
end

for loop latch

for (K = 7; K >= 0; K = K - 1)
begin: FLOW
  if (!Copy_Enable[K])
    begin
      disable FLOW;
    end
  else
    begin
      Data_Out[K] = Data_In[K];
    end

end

Copy_Enable[K]가 1'b0이 되면 latch 발생

Data_Out = 8'b0;
for (K = 7; K >= 0; K = K - 1)
begin: FLOW
  if (!Copy_Enable[K])
    begin
      disable FLOW;
    end
  else
    begin
      Data_Out[K] = Data_In[K];
    end

end

---

Flip Flop

always @(negedge Clock)
begin
  Data_Out <= Data_In;
end

Negative edge triggered FF이 target technology에 있으면 그거 쓰고,
없으면 Not gate 추가해서 합성함

reg Data_Out;
reg Intermediate_Variable;

always @(posedge Clock)
begin
  Intermediate_Variable = In_A & In_B;
  Data_Out <= Intermediate_Variable;
end

And gate의 연산 결과인 Intermediate_Variable이 FF의 D로 들어감.

reg Data_Out;
reg Intermediate_Variable;

always @(posedge Clock)
begin
  Intermediate_Variable <= In_A & In_B;
  Data_Out <= Intermediate_Variable;
end

FF 2개 생성
하나는 And gate의 연산 결과가 D 핀으로, Intermediate_Variable이 Q핀으로 나오는 FF
나머지 하나는 Intermediate_Variable이 D핀으로, Data_Out이 Q핀으로 연결된 FF

---

always @(posedge Clock)
begin

  if (Enable)
    begin
      Toggle <= ~ Toggle;
    end
end

XOR gate 이용하여 합성

always @(posedge Clock)
begin

  if (Enable_A)
  
    begin
      D_Out <= In_A;
    end
    
  else
  
    begin
      D_Out <= In_B;
    end

end

target technology에 enable pin이 있는 FF 있으면 그거 사용
없으면 mux등을 이용하여 합성

• hdlin_ff_always_sync_set_reset

  • When set to true synthesis is directed to automatically check the coding style for synchronous set and reset conditions of flip-flops
  • default value is false
  • .synopsys_dc.setup 에서 true로 바꿀 수 있음

• sync_set_reset"signal_name_list"

  • Directs the synthesis tool to check the signals in the list to determine if they synchronously set or reset the design
  • hdlin_ff_always_sync_set_reset defualt 값이 false기에 사용됨

// synopsys sync_set_reset "Reset"
always @(posedge Clock)
begin

  if (Reset)
    begin
      Data_Out <= 1'b0;
    end
  else
    begin
      Data_Out <= Data_In;
    end
    
end

이름에 상관 없이 형태에 따라 정해짐

• hdlin_ff_always_async_set_reset

  • When set to true synthesis is directed to automatically check for asynchronous set and reset conditions of flip-flops
  • Defualt is true
  • initialization file, .synopsys_dc.setup에서 바꿀 수 있음

• async_set_reset"signal_name_list"

  • Directs the synthesis tool to check the signals in thelist to determine if they asynchronously set or reset the design
  • hdlin_ff_always_async_set_reset의 기본값이 true기 때문에 사용하는거 추천 안함

---

always @(posedge Clock, posedge cond_1, negedge Cond_2)
begin

  if (Cond_1)
    // Asynchronously controlled
  else if (Cond_2)
    // Asynchronously controlled
  else
    // Synchronously controlled
end

edge와 non-edge events 가 같은 event list에 있는거 합성 안함
edge conditoin과 polarity of the teseted condition이 다르면 합성 안함

always @ (posedge Clock, negedge Reset_N)
begin
  if (!Reset_N)
    begin
      Data_Out <= 8'b0;
    end
  else if (Enable_AB)
    begin
      Data_Out <= In_A + In_B;
    end
  else if (Enable_CD)
    begin
      Data_Out <= In_C + In_D;
    end
  else if (Enable_EF)
    begin
      Data_Out <= In_E + In_F;
    end
  else
    begin
      Data_Out <= In_G + In_H;
    end
end

가독성 안좋음
Reset_N은 asynchronous reset이고 나머지 Enable 신호들은 synchronous 신호들임

always @ (posedge Clock, negedge Reset_N)
begin
  if (!Reset_N)
    begin
      Data_Out <= 8'b0;
    end
  else 
    if (Enable_AB)
      begin
        Data_Out <= In_A + In_B;
      end
    else if (Enable_CD)
      begin
        Data_Out <= In_C + In_D;
      end
    else if (Enable_EF)
      begin
        Data_Out <= In_E + In_F;
      end
    else
      begin
        Data_Out <= In_G + In_H;
      end
end

clock에 synchronous 되는 신호들은 else 밑에 한꺼번에 넣어주기.

// synopsys on_hot "Set, Reset"
always @(posedge Clock, posedge Reset, posedge Set)
begin

  if (Set)
    begin
      Data_Out <= 1'b1;
    end
  else if (Reset)
    begin
     Data_Out <= 1'b0;
    end
  else
    begin
      Dat_Out <= Data_In;
    end
end

Without the attribute one_hot a priority-checing sub circuit will be synthesized.
one_hot attribute 사용하면 Set, Reset에 동시에 1 들어왓을 때 동작을 예측할 수 없음.
The attribute one_cold may be used when the asserted state for both Set and Reset is 1'b0 and it is known that these two signals will not be asserted at the same time

`ifndef SYNTHESIS

  always @(Reset, Set)
    begin
    
      if (Reset & Set)
        begin
          $display ("one_hot violation for Reset and Set");
        end
    end
`endif

SYNTHESIS is a macro that is pre-defined in the Presto Verilog environment.
Usage of `ifndef SYNTHESIS causes this block of code to be bypassed by Presto Verilog.

---

Gated Clocks

Clock gating is a power reduction technique that shuts down the clock to large flip-flop blocks within a design when the outputs of these flip-flops are not needed.

Majority of power consumption in most designs is caused by the state changes of the clock

At high frequencies, power dissipation can be very significant
$Power = \frac{1}{2} \times Capacitance \times Voltage^2 \times Frequency$

assign Gated_Clock = Clock & Enable;

always @(posedge Gated_Clock, negedge Reset)
begin

  if (!Reset)
    begin
      Data_Out <= 8'b0;
    end
  else
    begin
      Data_Out <= Data_Out + 8'b1;
    end
end