class DelayNCycles(n: Int) extends Module {
val io = IO(new Bundle {
val in = Input(Bool())
val out = Output(Bool())
})
require(n >= 0)
def helper(n: Int, lastConn: Bool): Bool = {
if (n == 0) lastConn
else helper(n-1, RegNext(lastConn))
}
io.out := helper(n, io.in)
}
println(getVerilog(new DelayNCycles(2)))
반복문으로 생성한 것과, 재귀적으로 생성한 것 모두 동일한 결과를 내는 것을 확인할 수 잇다.
class MyPair(val a: Int, b: Int) {
def sum() = a + b
}
val mpc = new MyPair(3,4)
mpc.a
참고) val a를 붙이면, global이 되기에 통과하지만,
그냥 a:Int, b:Int 하면, mpc.a를 접근시 에러가 발생한다.
class MyCounter(maxVal: Int) extends Module {
val io = IO(new Bundle {
val en = Input(Bool())
val out = Output(UInt())
})
val count = RegInit(0.U(log2Ceil(maxVal+1).W))
when (io.en) {
when (count < maxVal.U) {
count := count + 1.U
} .otherwise {
count := 0.U
}
}
io.out := count
}
object MyCounter {
def apply(maxVal: Int) = new MyCounter(maxVal)
}
class MyCounter(maxVal: Int, en: Bool) {
val count = RegInit(0.U(log2Ceil(maxVal+1).W))
when (en) {
when (count < maxVal.U) {
count := count + 1.U
} .otherwise {
count := 0.U
}
}
}
object MyCounter {
def apply(maxVal: Int, en: Bool) = {
val mc = new MyCounter(maxVal, en)
mc.count
}
}
class CounterInstMod(n: Int) extends Module {
val io = IO(new Bundle {
val en = Input(Bool())
val count = Output(UInt())
})
io.count := MyCounter(n, io.en)
}
println(getVerilog(new CounterInstMod(4)))
class CounterInstMod(n: Int) extends Module {
val io = IO(new Bundle {
val en = Input(Bool())
val count = Output(UInt())
val limit = Output(Bool())
})
val (value, wrap) = Counter(io.en, n)
// val (value, wrap) = Counter(0 until n by 2, io.en)
io.count := value
io.limit := wrap
}
class Mag extends Bundle {
val m = UInt(4.W)
}
class OutMod(a: Int) extends Module {
val io = IO(Output(new Mag))
io.m := a.U
}
println(getVerilog(new OutMod(2)))
class Mag extends Bundle {
val m = Output(UInt(4.W))
}
class SignMag extends Mag {
val s = Output(Bool())
}
class PairSignMag extends Bundle {
val nums = Vec(2, new SignMag)
}
class OutMod(a: Int, b: Int) extends Module {
val io = IO(new PairSignMag)
io.nums(0).m := a.U
io.nums(0).s := false.B
io.nums(1).m := b.U
io.nums(1).s := false.B
}
println(getVerilog(new OutMod(3,4)))
class Handshake(w: Int) extends Bundle {
val ready = Input(Bool())
val data = Output(UInt(w.W))
}
class PassThru(w: Int) extends Module {
val io = IO(new Bundle {
val in = Flipped(new Handshake(w))
val out = new Handshake(w)
})
io.in <> io.out
}
println(getVerilog(new PassThru(4)))
// val o: Option[Int] = Some(4)
val o: Option[Int] = None
if (o.isDefined)
println(o.get)
else
println("empty")
class MaybePair(w: Int, hasY: Boolean) extends Bundle {
val x = Output(UInt(w.W))
val y: Option[UInt] = if (hasY) Some(Output(UInt(w.W))) else None
}
class OutMod(w: Int, a: Int, useY: Boolean) extends Module {
val io = IO(Output(new MaybePair(w, useY)))
io.x := a.U
if (useY)
// if (io.y.isDefined)
io.y.get := a.U
}
println(getVerilog(new OutMod(8,4,true)))