[Verilog 출력하기] circt 말고 chisel3 사용하기

공식문서 - Get me Verilog
에서는, import circt.stage.ChiselStage를 한 뒤에,

import circt.stage.ChiselStage
object VerilogMain extends App {
  ChiselStage.emitSystemVerilog(new HelloWorld)
}

를 하라고 되어있는데, 나는 아무리 해도 되지 않았다.
testbench 없이 소스코드로부터 바로 Verilog 뽑기를
90분 삽질 끝에 겨우 성공하여(...), 그 설정을 기록하고자 한다.

아 진짜 시간낭비 너무 억까야...

소스코드: ArbiterTest.scala

package mytest

import chisel3._
import chisel3.util.Decoupled

class InnerModule extends Module(){
  val io = IO(new Bundle {
	val intermediateDecoupled = Flipped(Decoupled(UInt(5.W)))
		val intermediateDecoupledOut = Decoupled(UInt())
		})
			io.intermediateDecoupled.ready := true.B
			io.intermediateDecoupledOut.valid := io.intermediateDecoupled.ready
			io.intermediateDecoupledOut.bits := io.intermediateDecoupled.bits
	}

class ArbiterTest(n: Int, m: Int) extends Module {
val io = IO(new Bundle {
	val in = Flipped(Decoupled(UInt(n.W)))
	val out = Decoupled(UInt(n.W))
		})

val innerModuler = Module(new InnerModule)
innerModuler.io.intermediateDecoupled <> io.in
io.out <> innerModuler.io.intermediateDecoupledOut

}

object ArbiterTest extends App{
	(new chisel3.stage.ChiselStage).emitVerilog(new ArbiterTest(32,32))
}

출력결과

module InnerModule(
  output       io_intermediateDecoupled_ready,
  input  [4:0] io_intermediateDecoupled_bits,
  output       io_intermediateDecoupledOut_valid,
  output [4:0] io_intermediateDecoupledOut_bits
);
  assign io_intermediateDecoupled_ready = 1'h1; // @[ArbiterTest.scala 11:58]
  assign io_intermediateDecoupledOut_valid = io_intermediateDecoupled_ready; // @[ArbiterTest.scala 12:63]
  assign io_intermediateDecoupledOut_bits = io_intermediateDecoupled_bits; // @[ArbiterTest.scala 13:68]
endmodule
module ArbiterTest(
  input         clock,
  input         reset,
  output        io_in_ready,
  input         io_in_valid,
  input  [31:0] io_in_bits,
  input         io_out_ready,
  output        io_out_valid,
  output [31:0] io_out_bits
);
  wire  innerModuler_io_intermediateDecoupled_ready; // @[ArbiterTest.scala 22:26]
  wire [4:0] innerModuler_io_intermediateDecoupled_bits; // @[ArbiterTest.scala 22:26]
  wire  innerModuler_io_intermediateDecoupledOut_valid; // @[ArbiterTest.scala 22:26]
  wire [4:0] innerModuler_io_intermediateDecoupledOut_bits; // @[ArbiterTest.scala 22:26]
  InnerModule innerModuler ( // @[ArbiterTest.scala 22:26]
    .io_intermediateDecoupled_ready(innerModuler_io_intermediateDecoupled_ready),
    .io_intermediateDecoupled_bits(innerModuler_io_intermediateDecoupled_bits),
    .io_intermediateDecoupledOut_valid(innerModuler_io_intermediateDecoupledOut_valid),
    .io_intermediateDecoupledOut_bits(innerModuler_io_intermediateDecoupledOut_bits)
  );
  assign io_in_ready = 1'h1; // @[ArbiterTest.scala 23:39]
  assign io_out_valid = innerModuler_io_intermediateDecoupledOut_valid; // @[ArbiterTest.scala 24:8]
  assign io_out_bits = {{27'd0}, innerModuler_io_intermediateDecoupledOut_bits}; // @[ArbiterTest.scala 24:8]
  assign innerModuler_io_intermediateDecoupled_bits = io_in_bits[4:0]; // @[ArbiterTest.scala 23:39]
endmodule

참고: build.sbt

// See README.md for license details.

def scalacOptionsVersion(scalaVersion: String): Seq[String] = {
  Seq() ++ {
    // If we're building with Scala > 2.11, enable the compile option
    //  switch to support our anonymous Bundle definitions:
    //  https://github.com/scala/bug/issues/10047
    CrossVersion.partialVersion(scalaVersion) match {
      case Some((2, scalaMajor: Long)) if scalaMajor < 12 => Seq()
      case _ => Seq("-Xsource:2.11")
    }
  }
}

def javacOptionsVersion(scalaVersion: String): Seq[String] = {
  Seq() ++ {
    // Scala 2.12 requires Java 8. We continue to generate
    //  Java 7 compatible code for Scala 2.11
    //  for compatibility with old clients.
    CrossVersion.partialVersion(scalaVersion) match {
      case Some((2, scalaMajor: Long)) if scalaMajor < 12 =>
        Seq("-source", "1.7", "-target", "1.7")
      case _ =>
        Seq("-source", "1.8", "-target", "1.8")
    }
  }
}

name := "fifo"

version := "3.3.1"
scalaVersion := "2.12.10"

crossScalaVersions := Seq("2.12.10", "2.11.12")

resolvers ++= Seq(
  Resolver.sonatypeRepo("snapshots"),
  Resolver.sonatypeRepo("releases")
)

addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.0" cross CrossVersion.full)

// Provide a managed dependency on X if -DXVersion="" is supplied on the command line.
val defaultVersions = Seq(
  "chisel-iotesters" -> "1.5.1",
  "chiseltest" -> "0.3.1"
  )

libraryDependencies ++= defaultVersions.map { case (dep, ver) =>
  "edu.berkeley.cs" %% dep % sys.props.getOrElse(dep + "Version", ver) }

scalacOptions ++= scalacOptionsVersion(scalaVersion.value)

javacOptions ++= javacOptionsVersion(scalaVersion.value)

...도대체 circt 얘는 뭐하는 애야?
firrtl의 업그레이드버전이며 chisel 3.5.0 이전에는 확실한 미지원이라는 것은 알겠는데,
정작 chisel 5.0.0으로 올려도 정작 돌아가지를 않아.