LEVEL0 - Basic logic gates

정다훈·2025년 6월 19일

Verilog study

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Using two input signals, create the output signals for the seven basic logic gates

(NOT, AND, NAND, OR, NOR, XOR, XNOR) 10min

module basic_gate
(
    input in_a,
    input in_b,
    output not_gate_out,
    output and_gate_out,
    output nand_gate_out,
    output or_gate_out,
    output nor_gate_out,
    output xor_gate_out,
    output xnor_gate_out
);

// TODO

endmodule

MY CODE

module basic_gate(
  input in_a,
  input in_b,
  output not_gate_out,
  output and_gate_out,
  output nand_gate_out,
  output or_gate_out,
  output nor_gate_out,
  output xor_gate_out,
  output xnor_gate_out
);

  assign not_gate_out = ~in_a;
  assign and_gate_out = in_a & in_b;
  assign nand_gate_out = ~(in_a & in_b);
  assign or_gate_out = in_a | in_b;
  assign nor_gate_out = ~(in_a | in_b);
  assign xor_gate_out = in_a ^ in_b;
  assign xnor_gate_out = ~(in_a ^ in_b);


endmodule

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