Verilog study

Using two input signals, create the output signals for the seven basic logic gates (NOT, AND, NAND, OR, NOR, XOR, XNOR). 10min

Karnaugh map - Introduction to Examples, About K-map, Problem Solving → 20min

L0-P03 Vector - Introduction to Examples, About vector & scalar, Problem Solving 10min

L0-P04 Condition- Introduction to Examples, About condition, Problem Solving(event)가 발생했을 때만 동작하는 logic, 시간기반 x

L0-P05 Multiplexer - Introduction to Examples, About Multiplexer, Problem Solving 10min

L0-P06 Adder - Introduction to Examples, About Adder, Problem Solving