[L0-P04] Condition- Introduction to Examples, About condition, Problem Solving

My Answer

module condition(
    input [1:0] sel,
    output reg [1:0] normal_if,   
    output reg [1:0] normal_case,   
    output     [1:0] normal_ternary,   
    output reg [1:0] latch_if,   
    output reg [1:0] latch_case   
); 

//TODO

//normal_if
always @(sel) begin
  if(sel == 0) normal_if[sel] = 1;
  else if(sel == 1) normal_if[sel] = 2;
  else if(sel == 2) normal_if[sel] = 3;
  else if(sel == 3) normal_if[sel] = 0;
end

//normal_case
always @(*) begin
  case (sel)
    0 : normal_case[sel] = 3;
    1 : normal_case[sel] = 0;
    2 : normal_case[sel] = 1;
    3 : normal_case[sel] = 2;
    default: 
  endcase
end

//latch_if
always @(sel) begin
  if(sel == 2) latch_if = 1;
end

//latch_case
always @(*) begin
  case(sel)
  0 : latch_case[sel] = sel;
  1 : latch_case[sel] = sel;
  2 : latch_case[sel] = sel;
  endcase

end

endmodule

Answer

module condition(
    input [1:0] sel,
    output reg [1:0] normal_if,   
    output reg [1:0] normal_case,   
    output     [1:0] normal_ternary,   
    output reg [1:0] latch_if,   
    output reg [1:0] latch_case   
); 

//TODO

//normal_if
always @(*) begin
  if(sel == 2'b00) normal_if[sel] = 2'd1;
  else if(sel == 2'b01) normal_if[sel] = 2'd2;
  else if(sel == 2'b10) normal_if[sel] = 2'd3;
  else if(sel == 2'b11) normal_if[sel] = 2'd0;
end

//normal_case
always @(*) begin
  case (sel)
    2'b00 : normal_case[sel] = 2'd3;
    2'b01 : normal_case[sel] = 2'd0;
    2'b10 : normal_case[sel] = 2'd1;
    2'b11 : normal_case[sel] = 2'd2;
    default: 
  endcase
end

// Ternary Operator
assign normal_ternary = (sel == 2'b00) ? (2'b10) :
                        (sel == 2'b01) ? (2'b11) :
                        (sel == 2'b10) ? (2'b00) : (2'b01);


//latch_if
always @(*) begin
  if(sel == 2'b10) latch_if = 2'd1;
end

//latch_case
always @(*) begin
  case(sel)
  2'b00 : latch_case[sel] = sel;
  2'b01 : latch_case[sel] = sel;
  2'b10 : latch_case[sel] = sel;
  endcase
end


endmodule

Lecture materials

Always Block

Basic Syntax

always @ (event) begin
	// Statements to execute
end

Combinational Logic

• (event)가 발생했을 때만 동작하는 logic, 시간기반 x

always @ (a or b) begin
	c = a & b;   // Output is updated whenever 'a' or 'b' changes
end

always @ (*) begin // *는 logic의 입력값이 변경되었을 때를 의미함
	c = a & b; 
end

Sequential Logic

D Flip-Flop implementation

always @ (posedge clk) begin // 시간기반
	q <= d; //store data on clock's rising edge
end

when using both clock and reset signals

always @ (posedge clk or negedge resetn) begin
	if(!resetn)
    	q <= 0;
    else
    	q <= d;
end

Blocking and Nonblocking

Blocking

always @(posedge clk) begin
	x = 1; // x is updated immediately
    y = x + 1; // y is calculated using the update value of x
end

Nonblocking

always @(posedge clk) begin
	x <= 1; //x will be updated at the end of this time step
    y <= x + 1; // y uses the previous value of x for calculation
end