LEVEL0 - MUX & DMUX

정다훈·2025년 6월 20일

Verilog study

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[L0-P05] Multiplexer - Introduction to Examples, About Multiplexer, Problem Solving 10min

module mux_demux(
    input mux_2to1_sel, 
    output mux_2to1_out,

    input  [1:0] mux_4to1_sel,  
    output [1:0] mux_4to1_out,  

    input            demux_1to2_sel,  
    input            demux_1to2_in,
    output reg [1:0] demux_1to2_out
);

//TODO


endmodule

Lecture materials

my Answer

module mux_demux(
  input mux_2to1_sel,
  output mux_2to1_out,

  input [1:0] mux_4to1_sel,
  output[1:0] mux_4to1_out,

  input       demux_1to2_sel,
  input       demux_1to2_in,
  output reg [1:0] demux_1to2_out

);

  assign mux_2to1_out = (mux_2to1_sel == 1'b0) ? (1'b1) : (1'b0);

  assign mux_4to1_out = (mux_4to1_sel == 2'd0) ? (2'd3) :
                        (mux_4to1_sel == 2'd1) ? (2'd2) :
                        (mux_4to1_sel == 2'd2) ? (2'd1) : (2'd0);

  always @(*) begin
    if(demux_1to2_sel == 1'b0) begin
      demux_1to2_out[0] <= demux_1to2_in;
      demux_1to2_out[1] <= 1'b0;
    end else begin
      demux_1to2_out[0] <= 1'b0;
      demux_1to2_out[1] <= demux_1to2_in;
    end                       
  end


endmodule

Answer

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