There are major hurdles of Pipelining. In this post, I will cover this major problems and solutions.
This hazard situation is occured when the next instruction cannot be executed in the following clock cycle.
An instruction depends on the results of a previous instruction still in pipeline.
For example, if we have these instructions, $s0 register cannot be used in sub instruction.
Problem with starting next instruction before first is finished.
We can solve the data hazard by using these methods.
We have to decide what actions we take. In this section, we will suppose that branch is not occured. So, we should make some architecture to flush when actually branch is ouccred.
These are the solutions about control hazard. If we stall, we can solve the control hazard problems.
We can optimized branch processing. However, there are two conditions.
We can reducing delay by moving branch execution to the ID stage. By using it, we can reduce the delay percent.
We can suppose that prediction always will be failed. If the prediction is wrong, then we must insert a bubble.
In the static branch prediction, we can choose three cases.
1. Never Branch
Assume that the branch never take place.
2. Always Branch
Assume that the branch always take place.
3. Predict by op-code
Decision is made based on the opcode.
We can use the space to remember the state of branch prediction. By using this other memory, we can make decision more easily.
This is a example about the dynamic branch prediction. We can keep the state of prediction.
If we use more memory slot, then we can use 2 bits to keep the state.