Lec 2 Performance

Seungyun Lee·4일 전

Computer Arch (Memory)

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Response Time and Throughput

  • Response time (also called execution
    time)
    • How long it takes to do a task
  • Throughput
    • Total work done per unit time
    • e.g., tasks/transactions/… per hour

Realative Performance

PerformancexPerformancey=Execution timeyExecution timex=n\frac {Performance_x} {Performance_y} = \frac {Execution\ time_y} {Execution\ time_x} = n

x,y 분자 분모 뒤바뀌는거 주의
x가 n만큼 y보다 빠르다 or 느리다

Measuring Execution Time

  • Elapsed time ( total excution time, wall time)
    - Total response time, Including all aspects

    • $ time ls: measure time under the file, ls(list files in derectory)
  • CPU Time
    - Time spent processing a given job

CPU Time

CPUTime=CPU Clock CyclesClock Rate=CPU Clock Cycle×CCTCPU_{Time} = \frac {CPU\ Clock\ Cycles} {Clock\ Rate} = CPU\ Clock\ Cycle \times CCT

거속시 관계처럼 유연하게 생각하기

Time=CCRate=CC×CCTTime = \frac{CC} {Rate} = CC \times CCT

Perfomance improved by

  • reducing number of clock cycle
  • increasing clock rate

Example

Computer A: 2GHz clock, 10s CPU time
• Designing Computer B
– Aim for 6s CPU time
– Can do faster clock, but causes 1.2 × clock cycles

• How fast must Computer B clock be?

CPI (Cycle per Insturction)

Instruction Count for a program

  • Determined by program, ISA and compiler
ClockCycle=Instruction Count×Cycle per InstructionClock Cycle = Instruction\ Count \times Cycle\ per\ Instruction
CPUTime=IC×CPIClock Rate=IC×CPI×CCTCPU_{Time} = \frac {IC \times CPI} {Clock\ Rate} = IC \times CPI \times CCT

ISA (instruction set Architecture)

  • defines types of instuctions

  • defines addressing mode

    	ALU: ADD R1, R2, R3 -> Register addressing mode
    	BNE R1, R2, L1
    	LD R, 8(R2) -> Indirect addressing mode

bracket means no data -> need to access memory

RISC (Reduced Inst Set Computing)

  • ADD R1 R2 R3: add R2, R3

CISC (Complex Inst Set Computing)

  • ADD R1, (R2), (R3): bring R2, R3 data from memory and add -> store to R1
  • include multiple instructions
  • inefficient
 j = b(i) + c(i)
 
 RISC - MIPS, ARM
 LD R4, (R2)
 LD R5, (R3)
 ADD R1, R4, R5
 
 CISC
 ADD R1, (R2), (R3)

Average cycles per instruction

  • Determined by CPU hardware
  • If different instructions have different CPI
profile
Design Verification engineer

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