VLSI Power
Vdd -> Capacitor -> Gnd
Dynamic power
- capacitance swithcing
- crowbar current
Static power
- Leakage current
relation with energy and delay
Low swing circuit
idea: let's change unitil vdd/3 so that we can save power
cons:
- we can not use normal gate
- weak at noise, can not tolerate noise, noise sensitive
Gated clocks
- stop the clock and put the logic to sleep
- put the and gate with enable signal
Increase length of transistors
- but sacrifice speed
Design Verification engineer