The Definitive Guide to the ARM® Cortex-M3 - 0

공부계획	날짜
CHAPTER 2 Overview of the Cortex-M3	5/23
CHAPTER 3 Cortex-M3 Basics	5/24
CHAPTER 4 Instruction Sets	5/25~5/26
CHAPTER 5 Memory Systems	5/30
CHAPTER 6 Cortex-M3 Implementation Overview	5/31
CHAPTER 7 Exceptions.	6/1
CHAPTER 8 The Nested Vectored Interrupt Controllerand Interrupt Control	6/2
CHAPTER 9 Interrupt Behavior	6/3

2.1 FUNDAMENTALS

The Cortex-M3 is a 32-bit microprocessor. It has a 32-bit data path, a 32-bit register bank, and 32-bit memory interfaces.
The processor has a Harvard architecture, which means that is has a separate insruction bus and data bus. This allows instruction and data accesses to take place at the same time, and as a result of this, the performance of the processor increases because data accesses do not afftect the insruction pipeline. This feature results in multiple bus interfaces on Cortex-M3, each with optimized usage and the ability to be used simultaneously. However, the instruction and data buses share the same memory space. In other words, you cannot get 8 GB of memory space just because you have separate bus interfaces.

For complex applications that require more memory system feaures, the Cortex-M3 processor has and option Memory Protection Unit, and it is possible to use an external cache if it's required.
Both little endian and bigendian memory systems are supported.

The Cortex-M3 processor includes a number of fixed internal debugging components.
These components provide debugging operation supports and features, such as breakpoints and watchpoints.

In addition, optional components provide debugging features, such as instruction trace, and various types of debugging interface.

2.2 REGISTERS
The Cortex-M3 processor has registers R0 through R15. R13 (the stack point) is banked, with only one copy of the R13 visible at a time.

2.2.1 R0-R12 : General-Purpose Registers
R0-R12 are 32-bit general-purpose registers for data operations. Some 16-bit Thumb instructions can only access sunset of these registers(low register, R0-R7).

2.2.2 R13 : Stack Pointers
The Cortex-M3 contains two stack pointers(R13). They are banked so that only one is visible at a time.
The two stack pointers are as follow:

• Main Stack Pointer(MSP) : The default stack pointer, used by the operation system( OS ) kernel and exceptin handlers.
• Process Stack Pointer (PSP) : Used by user application code

The lowest 2bits of the stack pointers are always 0, wich means they are always word aligned.
-> 주소값 항상 4씩 증가 감소

2.2.3 R14: The Link Register
When a subroutine is called, the return address is stored

2.2.4 R15 : The Program Counter
The program counter is the current program address. This register can be written to control the program flow.

2.2.5 Special Registers

The Cortex-M3 processor also has a number of special registers. They are as follows :

• Program Status Regusters(PSRs)
• Interrupt Mask registers(PRIMASK, FAULTMASK, and BASEPRI)
• Control register(CONTROL)

These registers have special functions and can be accessed only by special instructions, They cannot be used for normal data processing(see table 2.1).

Register	Function
xPSR	Provide arithmetic and logic processing flags (zero flag and carry flag),execution status, and current executing interrupt number
PRIMASK	Disable all interrupts except the nonmaskable interrupt(NMI) and hard fault
FAULTMASK	Disable all interrupts except the NMI
BASEPRI	Disable all interrupts of specific priority level of lower prioiry level
CONTROL	Define privileged status and stack pointer selection

2.3 OPERATION MODES

The Cortex-M3 processor has two modes and two privilege levels. The operation modes(Thread mode and handler mode) determine whether the processor is running a normal program or running an exception handler like an interrupt handler or system exception handler. The privilege levels (Privileged level and user level) provide a mechanism for safeguarding memory accesses to critical regions as well as providing a basic security model.

When the processor is unning a main program (thread mode), it can be either in a privileged state or a user state, but exception handlers can only be in a privileged state. When the processor exits reset, it is in thread mode, with privileged access rights.
In the privileged state, a program has access to all memory ranges(except when prohibited by MPU settings) and can use all supported instructions.

Software in the privileged access level can switch the program into the user acess level using the control register. When an exception takes place, the processor will always switch back to the privileged state and return to the privious state when exiting the exception handler. A user program cannot change back to the privileged state by writing to the control register. It has to go through an exception handler that programs the control register( see Figure 2.5). It has to go through an exception handler that programs the control register to switch the processor back into the privileged access level when returning to thread mode.

특권 액세스 수준에서 동작하는 소프트웨어는 제어 레지스터를 사용하여 프로그램을 사용자 액세스 수준으로 전환할 수 있습니다. 예외가 발생하면 프로세서는 항상 특권 상태로 전환되고 예외 처리기를 종료할 때 이전 상태로 돌아갑니다. 사용자 프로그램은 제어 레지스터에 쓰는 것만으로 특권 상태로 다시 전환할 수 없습니다. 스레드 모드로 돌아갈 때 프로세서를 특권 액세스 수준으로 전환하기 위해 예외 처리기를 거쳐야 합니다

Ther separation of privilege and user levels improces system reliability by preventing system configuration registers from being accessed or chnaged by some untrusted programs. If an MPU is available, it can be used in conjuction with privilege levels to protect critical memory locations, such as programs and data for OSs.

For example, with privileged accesses, usually used by the OS kernel, all memory locations can be accessed(unless prohibited by MPU setup). When the OS launches a user application, it is likely to be executed in the user access level to protect the system from failing due to a crash of untrusted user programs.

사용자 액세스 수준에서 실행되는 응용 프로그램은 제한된 권한을 갖기 때문에 시스템 리소스에 무작위로 접근하거나 손상시키는 일을 방지할 수 있습니다. 이를 통해 시스템의 안정성과 보안이 강화됩니다. 운영 체제는 사용자 액세스 수준에서 실행되는 응용 프로그램을 감시하고 제어하여 필요한 시스템 리소스에만 접근할 수 있도록 합니다. 이 방식으로 시스템은 사용자 프로그램의 오동작으로 인한 영향을 최소화하고 안정성을 유지할 수 있습니다.

2.4 THE BUILT_IN NESTED VECTORED INTERRUPT CONTROLLER

The Cortex-M3 processor includes an interrupt controller called the Nested Vectored Interrupt Controller(NVIC). It is closely coupled to the processor core and provides a number of features as follow:

• Nested interrupt support
• Vector interrupt support
• Dynamic priority changes support
• Reduction of interrupt latency
• Interrupt masking

2.4.1 Nested Interrupt Support
The NVIC provides nested interrupt support. All the external interrupts and most of the system exceptions can be programmed to different priority levels. When an interrupt occurs, the NVIC compares the priority level. If the priority of the new interrupt is higher than the current level, the interrupt handler of the new interupt will override the current runing task

2.4.2 Vectored interrupt Support
The Cortex-M3 processor has vectored interrupt support. When an interrupt is accepted, the starting address of interrupt service routine(ISR) is located from a vector table in memory.

2.4.3 Dynamic Priority Changes Support
Priority levels of interrupts can be changed by software during run time. Interrupts that are being serviced are blocked from further activation until the ISR is completed, so their priority can be changed without risk of accidental reentry.

2.4.4 Reduction of interrupt latency
The Cortex-M3 processor also includes a number of advanced features to lower the interrupt latency.
These include automatic saving and restoring some register contents, reducing delay in switching from one ISR to another, and handling of late arive.

2.4.5 Interrupt Masking
Interrupts and system exception can be masked based on their prioirty level or masked completely using the interrupt masking registers BASEPRI,PRIMASK, and FAULTMASK. They can be used to ensure that ime critical task can be finished on time without being interrupted.
-> 이러한 인터럽트 마스킹 메커니즘을 사용하면 시간이 중요한 작업을 완료하는 동안 인터럽트로부터 보호되고, 예기치 않은 중단으로 인한 문제를 방지할 수 있습니다. 그러나 인터럽트를 마스킹하면 시스템의 반응성이 감소할 수 있으므로, 마스킹된 인터럽트를 적절하게 관리하는 것이 중요합니다.

2.5 THE MEMORY MAP

The Cortex-M3 has a predefined memory map. This allows the built-in peripherals, such as the interrupt controller and the debug components, to be accessed by simple memory access instrunctions. Thus, most system features are accessible in C program code. The predefined memory map also allows the Cortex-M3 processor to be highly optimized for speed and ease of integration in system on a chip designs.

Overall, the 4 GB memory space can be divided into ranges as shown in Figure 2.6.

The Cortex-M3 design has an internal bus infrastructure optimized for this memory usage. In addition , the design allows these regions to be used differently. For example, data memory can still be put into the CODE region, and program code can be executed from an external Random Access Memory (RAM) region.

The system-level memory region contains the interrupt controller and the debug components. These devices have fixed addresses, detail in chapter 5. By having fixed addresses for these peripherals, you can port applications between differen Cortex-M3 products much more easily.

2.6 THE BUS INTERFACE
There are several bus interfaces on the Cortex-M3 processor. They allow the Cortex - M3 to carry instruction fetcheds and data accesses at the same time. The main bus interfaces are as follow:

• Code memory buses
• System bus
• Private peripheral bus

The code memory region access is carried out on the code memory buses, which physically consist of two buses, one called I-Code and other called D-Code. These are optimized for instruction fetches for best instruction execution speed.

The system bus is used to access memory and peripherals. This provides access to the Static RAM, external RAM, external devices, and part of the system level memory regions.

The private peripheral bus provides access to a part of the system level memory dedicated to private peripherals, such as debugging components.

2.7 THE MPU
The Cortex-M3 has an optional MPU. This unit allows access rules to be set up for privileged access and user program access. When an access rule is violated, a fault exception is generated, and the fault exception handler will be albe to analyze the problem and correct it, if possible.

The MPU can be used in various ways. In common scenarios, the OS can set up the MPU ti protect dta use by the OS kernel and other privieged processes to be protected from untrusted user programs.

The MPU can also be used to make memory regions read-only, to prevent accidental erasing of data or to isolate memory regions between different tasks in a multitasking system. Overall, it can help make embedded systems more robust and reliable.

The MPU feature is optional and is determined during the implementation stage of the microcontroller or SoC design. For more information on the MPU

2.8 THE INSTRUCTION SET

The Cortex-M3 supports the Thumb-2 instruction set. This is one of the most important features of the Cortex-M3 processor because it allows 32-bit instructions and 16-bit instructions to be used together for high code density and high efficiency. It is flexible and powerful yet easy to use.

In previous ARM processors, the CPU had two operation state : a 32-bit ARM state and a 16-bit Thum state. In the ARM state, the instructions are 32bits and can execute all supported instrctions with very high performance. In the Thumb state, the instruction are 16 bits, so there is a much higher instruction code density, but the Thumb state does not have all the functionality of ARM instructions and may require more instructions to complete certain types of operation.

To get the best of both world, many applications have mixed ARM and Thumb codes. However, the mixed-code arrangement does not always work best. There is overhead(in terms of bost excution time and instruction space) to switch etween the states, and ARM and Thubm codes might need to be compiled separately in different files.

Thumb 상태는 주로 코드 크기를 줄이고 메모리 사용량을 최적화하는 데 사용됩니다. 16비트 Thumb 명령어는 32비트 ARM 명령어보다 작은 공간을 차지하므로 프로그램의 크기를 줄일 수 있습니다. 이는 주로 제한된 메모리 용량을 가진 장치에서 유용합니다.

그러나 Thumb 상태는 ARM 명령어의 모든 기능을 갖지는 않습니다. 따라서 특정 작업을 수행하기 위해서는 ARM 상태로 전환해야 할 수도 있습니다. Thumb 명령어는 보다 간단하고 짧은 형식을 가지므로, Thumb 상태에서는 일부 작업을 완료하기 위해 더 많은 명령어가 필요할 수 있습니다. 이로 인해 Thumb 상태에서의 성능은 ARM 상태에 비해 상대적으로 낮을 수 있습니다.

최신의 ARM 프로세서에서는 Thumb 상태 대신 Thumb-2 상태가 도입되었습니다. Thumb-2 상태는 16비트와 32비트 명령어를 모두 지원하여 명령어 코드의 밀도와 성능을 높이는 장점을 가지고 있습니다.

With the introduction of the Thumb 2 instruction set, it is now possibe to handle all processing requriements in one operation state. There is no need to switch between the two. In fact, the Cortex-M3 does not support the ARM code. Even interrupts are now handled wit the Thumb state. Since there is no need to switch between state. The Cortex-M3 processor has a number of advatages over traditional ARM processors, such as :

• No state switching overhead, saving both execution time and instruction space

• No need to separate ARM code and Thumb code source files, making software development and maintenance easier

• It's easier to get the best efficiency and performance, in turn making it easier to write software, because there is no need to worry about switching code between ARM and Thumb to try to get the best density/performance

상태 전환 오버헤드가 없으므로 실행 시간과 명령어 공간을 모두 절약할 수 있습니다.
ARM 코드와 Thumb 코드 소스 파일을 분리할 필요가 없으므로 소프트웨어 개발과 유지 보수가 더욱 쉬워집니다.
최적의 효율성과 성능을 쉽게 얻을 수 있으므로 소프트웨어 작성이 용이해집니다. ARM과 Thumb 간에 코드를 전환하여 최상의 밀도/성능을 얻기 위해 코드를 관리할 필요가 없습니다.

The Cortex-M3 processor has a number of interesting and powerful instructions. Here are a few examples :

• UFBX,BFI, and BFC : Bit field extract, insert, and clear instructions
• UDIV and SDIV : Unsigned and signed divide instructions
• WFE, WFI and SEV : Wait For Event, Wait For Interrupts, and Send-Event; these allow the processor to enter sleep mode and to handle task synchronization on multiprocessor systems.
• MSR and MRS : Move to special register from general-purpose register and move special register to general purpose register; for access to the special registers.

Since the Cortex-M3 processor supports the Thumb-2 instruction set only, existing program code for ARM needs to be ported to the new architecture. Most C applications simply need to be recompiled using new compilers that cupport the Cortex-M3. Some assembler codes need modification and porting to tuse the new architecture and the new unified assembler framwork.

SIMD is not implemented on the Cortex-M3. In addition, a few Thumb instructions are not supported, such as Branch with Link and Exchange(BLX) with immediate( used to switch processor state from Thumb to ARM), a couple of change process state(CPS) instructions, and the SETEND(set endian) instructions, which were introduced in

2.9 INTERRUPTS AND EXCEPTIONS

The Cortex M3 implements a new exception model.

enabling very efficient