생성일: 2021년 10월 16일 오후 9:42

Issues in Pipeline Design

• Balancing work in pipline stages
  • How many stages and what is done in each stage
• Keeping the pipeline correct, moving, and full in the presence of events that disrupt pipeline flow
• Handling exceptions, interrputs
• Improving pipeline throughput

Pipeline Hazards‼️

Hazards는 지정된 clock cycle동안 다음 명령어가 실행되지 않게 할 수 있다.

1. Structural hazards
   • Multiple instructions use a single HW resource
2. Data hazards
   • Instructions depends on result of prior instruction still in the pipeline
3. Control hazards
   • A branch in the control flow makes ambiguous what is the next instruction to fetch

Solution

Common solution = stall the pipeline until the hazard is resolved, inserting one or more "bubbles" in the pipeline

• Pipeline interlock logic detects hazards and fixes them simple solution
• Better solution : partial stall
• Best solution : remove hazard sources

Pipeline의 stall 조건

Stall = A condition when pipline stops moving

• Resource contention(리소스 경합)
• Dependences(between instructions)
  • Data

    • Flow dependence (read after write)

    • Output dependence (write aftter write)

    • Anti dependence (write after read)

      이 3가지 타입의 data dependence 가 stall을 발생 시킬수 있다 ⇒ 전부 semantics of program이 올바른지 확인해야 함

      

  • Control
    • Question: What should the fetch PC be in the next cycle?
    • Answer: The address of the next instruction
    • If the instruction that is fetched is a control-flow instruction:
      How do we determine the next Fetch PC?
• Long-latency (multi-cycle) operations

Structual Hazards

Memory나 Floating point 연산에서 주로 발생

• 비용 절감을 위해 CPU는 메모리에 대한 단일 interface로 설계될 수 있다
• 이 interface는 IF 동안 항상 사용 됨
• Load 또는 Store operations를 위한 MEM 중에도 사용 됨
• Load or Store이 MEM 단계에 도달하면 IF 단계의 instruction이 stall 되어야만 함

• Dealing with Structural Hazards
  • Stall
    • 장: Low cost, simple
    • 단: Increase CPI
    • Use for rare case since stalling has perforamance effect
  • Pipeline hardware resource
    • 장: useful for multi-cycle resources, good performance
    • 단: sometimes complex e.g. Ram
  • Replicate resource (e.g. Havard Architecture)
    • 장: good performance
    • 단: increases cost (+ maybe interconnect delay)
    • Useful for cheap or divisible resources
• Strctural hazards are reduced with these rules
  1. Each instruction uses a resource at most once
  2. Always use the resource in the same pipeline stage
  3. Use the resource for one cycle only

Data Hazards

• These occur when at any time, there are instructions active in pipeline that need to access the same data locations

• In pipeline architecture, instructions sometimes could not use right data for its processing without proper handling

• Read After Write (RAW) - Flow dependence

  Instruction J tries to read operand before Instruction I writes it

  

  Caused by a “Dependence” (in compiler nomenclature). This hazard results from an actual need for communication

  • Solution
    • Hardware detects RAW and stalls
    • Assumes register written then read each cycle
  • Minimizing RAW stalls
    • Bypass/forward/shortcircuit (We will use the word “forward”)
    • Use data before it is delivered to the register
    • Crucial for common RAW hazards

• Write After Read (WAR) - Anti dependence

  Instruction J tries to write operand before Instruction I reads I

  

  This results from reuse of the name “r1”

  • Can’t happen in MIPS 5 stage pipeline

• Write After Write (WAW) - Output dependence

  Instruction J tries to write operand before Instruction I writes it

  

  This also results from the reuse of name “r1”

  • Can’t happen in MIPS 5 stage pipeline

Control Hazards

• if CPI = 1, 30% branch, Stall 3 cycles ⇒ new CPI = 1.9 (매우 성능 하락)
• Solution to prevent these increase
  • Determine branch taken or not sooner, AND
  • Compute taken branch address earlier

Five Branch Hazard Alternatives

1. Stall until branch direction is clear
2. Predict Branch Not Taken
   1. Execute successor instructions in sequence
   2. 47% MIPS branches not taken on average
   3. PC+4 already calculated, so use it to get next instruction
3. Predict Branch Taken
   1. 53% MIPS branches taken on average
   2. But haven’t calculated branch target address in MIPS
4. Execute Both Paths
5. Delayed Branch

Branch Prediction으로 연결됨