8. Single-cycle MIPS Processor 2

생성일: 2021년 10월 10일 오후 7:51

Any instruction set can be implemented in many different ways.

• single-cycle implementation : all operations take the same amount of time - a single cycle.
• pipelined implementation : a processor can overlap the execution of several instructions, potentially leading to big performance gains.

Executing an R-type instruction

Decoding I-type instructions

Final datapath

Control path

• The control unit is responsible for setting all the control signals so that each instruction is executed properly
  • The control unit's input is 32-bit instruction word
  • The outputs are values for the blue control signals in the datapath
• Most of the signals can be generated from the instruction opcode alone, and not the entire 32-bit word.

Generating control signals

• The control unit needs 13 bits of input
  • 6 bits ⇒ opcode
  • 6 bits ⇒ func field
  • It also needs the Zero output of the ALU
• The control unit generates 10 bits of output

Top level block diagram for MIPS CPU

Summary

• A datapath contains all the functional units and connections necessary to implement an instruction set architecture.
• The control unit tells the datapath what to do, based on the instruction that’s currently being executed.