7. Single-cycle MIPS processor

생성일: 2021년 10월 3일 오후 9:08

• In a basic single-cycle implementation: all operations take the same amount of time-a single cycle.
• In a pipelined implementation, a processor can overlap the execution of several instructions, potentially leading to big performance gains.

I will discuss three types of instructions (R-type, I-Type, J-Type) separately.

All instructions will execute in the same amount of time; this will determine the clock cycle time for our performance equations.

Computers are state machines

computers are just a big fancy state machine

• Registers, memory, hard disks and other storage form the state.
• The processor keeps reading and updating the state, according to the instructions in some program

Finite state machine

Finite state machine is a function F:(S x I) → (S x O)

• S = {s0, s1, ⋯ , sn−1} is a finite set of states
• I = {i0, i1, ⋯ , ik−1} is a finite set of input values
• O = {o0, o1, ⋯ , om−1} is a finite set of output values

Instruction fetching

• the program counter or PC register holds the address of the current instruction
• MIPS instructions are each of 4 bytes long, so the PC should be incremented by 4 to read the next instruction in sequence.

Decoding instructions (R-type)

encoding 된 R 타입 instruction

• Our register file stores 32 bit values

  • Each register specifier is 5 bits long
  • You can read from 2 register at a time
  • RegWrite is 1 if a register should be written

• Opcode determines ALUOp

  

• Executing an R-type instruction