[Semicon Insights #4] RISC-V, NPU

oerreoยท2026๋…„ 4์›” 27์ผ

Semicon Insights

๋ชฉ๋ก ๋ณด๊ธฐ
4/14

๐Ÿ’กToday Keyword

  • RISC-V Ecosystem Expansion

  • Nvidia's Agentic AI-CPU Strategy

  • Memory-Centric AI Inference

  • FPGA-based RISC-V Prototyping

  • AI-Driven Chip Verification

๐Ÿ“ขNvidia, SiFive ํˆฌ์ž๋ฅผ ํ†ตํ•ด NVLink์™€ RISC-V ๊ฒฐํ•ฉ ๊ฐ€์†ํ™”

  • โœ”๏ธ๋ฐœํ‘œ ๊ธฐ์—…: Nvidia, SiFive

  • โœ”๏ธ๋ฐœํ‘œ ์ผ์ž: 26.04.16

  • โœ”๏ธ๋ฐœํ‘œ ๊ธฐ์ˆ  ๋ถ„์•ผ: CPU ์•„ํ‚คํ…์ฒ˜ ๋ฐ ๊ณ ์† ์ธํ„ฐํŽ˜์ด์Šค (NVLink)

  • โœ”๏ธํ•ต์‹ฌ ๋‚ด์šฉ
    1๏ธโƒฃ Nvidia๊ฐ€ SiFive์˜ ์‹œ๋ฆฌ์ฆˆ G ํŽ€๋”ฉ์— ์ฐธ์—ฌํ•˜๋ฉฐ RISC-V ์•„ํ‚คํ…์ฒ˜๋ฅผ ์ž์‚ฌ์˜ NVLink ์ƒํƒœ๊ณ„๋กœ ๋Œ์–ด๋“ค์ด๋Š” ์ „๋žต์  ์›€์ง์ž„์„ ๋ณด์ž„.
    2๏ธโƒฃ Agentic AI์˜ ๋ถ€์ƒ์œผ๋กœ ์ธํ•ด CPU๊ฐ€ ๋‹ค์‹œ AI ์Šคํƒ์˜ ์ค‘์‹ฌ๋ถ€๋กœ ์ด๋™ํ•จ์— ๋”ฐ๋ผ, ์œ ์—ฐํ•œ RISC-V ๊ธฐ๋ฐ˜ ์ปค์Šคํ…€ CPU ์„ค๊ณ„์˜ ์ค‘์š”์„ฑ์ด ์ปค์ง€๊ณ  ์žˆ์Œ.
    3๏ธโƒฃ ๋ฐ์ดํ„ฐ ์„ผํ„ฐ ๋‚ด์—์„œ ์ „ํ†ต์ ์ธ CPU์˜ ํ•œ๊ณ„๋ฅผ ๊ทน๋ณตํ•˜๊ณ , AI ์›Œํฌ๋กœ๋“œ์— ์ตœ์ ํ™”๋œ ์ดˆ๊ณ ์† ์—ฐ์‚ฐ ๋ฐ ํ†ต์‹  ์•„ํ‚คํ…์ฒ˜๋ฅผ ๊ตฌ์ถ•ํ•˜๊ธฐ ์œ„ํ•œ ํฌ์„์œผ๋กœ ํ•ด์„๋จ.

๐Ÿ“ขSKํ•˜์ด๋‹‰์Šค, ์ŠคํŽ˜์ธ Semidynamics ํˆฌ์ž๋ฅผ ํ†ตํ•œ ๋ฉ”๋ชจ๋ฆฌ ์ค‘์‹ฌ AI ์นฉ ๊ฐ•ํ™”

  • โœ”๏ธ๋ฐœํ‘œ ๊ธฐ์—…: SKํ•˜์ด๋‹‰์Šค, Semidynamics

  • โœ”๏ธ๋ฐœํ‘œ ์ผ์ž: 26.04.08

  • โœ”๏ธ๋ฐœํ‘œ ๊ธฐ์ˆ  ๋ถ„์•ผ: ๋ฉ”๋ชจ๋ฆฌ ์ค‘์‹ฌ AI ๊ฐ€์†๊ธฐ ๋ฐ RISC-V ์„ค๊ณ„

  • โœ”๏ธํ•ต์‹ฌ ๋‚ด์šฉ
    1๏ธโƒฃ SKํ•˜์ด๋‹‰์Šค๊ฐ€ ๋ฉ”๋ชจ๋ฆฌ ๋Œ€์—ญํญ ๋ณ‘๋ชฉ ํ˜„์ƒ์„ ํ•ด๊ฒฐํ•˜๋Š” RISC-V IP ์„ค๊ณ„์‚ฌ์ธ Semidynamics์— ์ „๋žต์  ํˆฌ์ž๋ฅผ ๋‹จํ–‰ํ•จ.
    2๏ธโƒฃ Semidynamics์˜ ๋…์ž ๊ธฐ์ˆ ์ธ Gazzillion์€ LLM ์ถ”๋ก  ์‹œ ๋ฐœ์ƒํ•˜๋Š” ๋ฉ”๋ชจ๋ฆฌ ์ง€์—ฐ์„ ํšจ๊ณผ์ ์œผ๋กœ ๊ด€๋ฆฌํ•˜์—ฌ ๋ฐ์ดํ„ฐ ์ฒ˜๋ฆฌ ํšจ์œจ์„ ๋†’์ž„.
    3๏ธโƒฃ ์ปดํ“จํŒ… ๋Šฅ๋ ฅ๋ณด๋‹ค ๋ฉ”๋ชจ๋ฆฌ ์šฉ๋Ÿ‰๊ณผ ๋ฐ์ดํ„ฐ ์ด๋™์ด AI ๊ฒฝ์ œ์„ฑ์„ ๊ฒฐ์ •ํ•˜๋Š” ์‹œ๋Œ€์— ๋งž์ถ”์–ด, HBM๊ณผ ๊ฒฐํ•ฉ๋œ ์ตœ์ ์˜ AI ์ธํ”„๋ผ ์นฉ ์„ค๊ณ„๋ฅผ ๋ชฉํ‘œ๋กœ ํ•จ.

๐Ÿ“ข์ค‘๊ตญ ํœด๋จธ๋…ธ์ด๋“œ ๋กœ๋ด‡ ์—…๊ณ„, Nvidia Jetson ๋Œ€์‹  RISC-V AI CPU ์ฑ„ํƒ ํ™•์‚ฐ

  • โœ”๏ธ๋ฐœํ‘œ ๊ธฐ์—…: ์ค‘๊ตญ ๊ณผํ•™์›(CAS) ๋ฐ 'Linglong 2.0' ์ œ์กฐ์‚ฌ

  • โœ”๏ธ๋ฐœํ‘œ ์ผ์ž: 26.04.22

  • โœ”๏ธ๋ฐœํ‘œ ๊ธฐ์ˆ  ๋ถ„์•ผ: ์ง€๋Šฅํ˜• ์—ฃ์ง€ ์ปดํ“จํŒ… ๋ฐ ์˜คํ”ˆ์†Œ์Šค ํ•˜๋“œ์›จ์–ด

  • โœ”๏ธํ•ต์‹ฌ ๋‚ด์šฉ
    1๏ธโƒฃ ์ตœ๊ทผ ๋ฒ ์ด์ง•์—์„œ ์—ด๋ฆฐ ๋กœ๋ด‡ ๋Œ€ํšŒ์—์„œ Linglong 2.0์„ ํฌํ•จํ•œ ๋‹ค์ˆ˜์˜ ํœด๋จธ๋…ธ์ด๋“œ ๋กœ๋ด‡์ด ๊ธฐ์กด Nvidia ์†”๋ฃจ์…˜ ๋Œ€์‹  ๋…์ž์ ์ธ RISC-V AI CPU๋ฅผ ํƒ‘์žฌํ•จ.
    2๏ธโƒฃ ์ค‘๊ตญ์˜ ๋ฐ˜๋„์ฒด ์ž๊ธ‰์ž์กฑ ์ „๋žต์˜ ์ผํ™˜์œผ๋กœ, ์˜คํ”ˆ์†Œ์Šค ํ”„๋กœ์„ธ์„œ์ธ Xiangshan๊ณผ Ruyi OS๋ฅผ ๊ฒฐํ•ฉํ•œ ํ†ตํ•ฉ ์นฉ ํ”Œ๋žซํผ ๊ตฌ์ถ•์ด ๊ฐ€์†ํ™”๋˜๊ณ  ์žˆ์Œ.
    3๏ธโƒฃ ํŠนํžˆ ์—ฃ์ง€ ๋‹จ์˜ ๋””์ง€ํ„ธ ํšŒ๋กœ ์„ค๊ณ„์—์„œ ๋†’์€ ์ž์œ ๋„์™€ ์ €์ „๋ ฅ ์„ฑ๋Šฅ์„ ์ œ๊ณตํ•˜๋Š” RISC-V๊ฐ€ ๊ณ ์„ฑ๋Šฅ ๋กœ๋ณดํ‹ฑ์Šค ์ œ์–ด์˜ ํ•ต์‹ฌ์œผ๋กœ ์ž๋ฆฌ ์žก๊ณ  ์žˆ์Œ.

๐Ÿ“ขQualcomm, AI ๊ธฐ๋ฐ˜ ์„ค๊ณ„ ๊ฒ€์ฆ์„ ํ†ตํ•ด GPU ๋ฐ NPU ๊ฐœ๋ฐœ ์†๋„ ํš๊ธฐ์  ๋‹จ์ถ•

  • โœ”๏ธ๋ฐœํ‘œ ๊ธฐ์—…: Qualcomm, Synopsys

  • โœ”๏ธ๋ฐœํ‘œ ์ผ์ž: 26.04.20 (์‚ฌ๋ก€ ๋ถ„์„ ์—…๋ฐ์ดํŠธ)

  • โœ”๏ธ๋ฐœํ‘œ ๊ธฐ์ˆ  ๋ถ„์•ผ: ๋””์ง€ํ„ธ ํšŒ๋กœ ์„ค๊ณ„ ์ž๋™ํ™” (EDA/Verification)

  • โœ”๏ธํ•ต์‹ฌ ๋‚ด์šฉ
    1๏ธโƒฃ ํ€„์ปด์ด GPU์™€ ๊ฐ™์ด ๋ณ‘๋ ฌ์„ฑ์ด ๋†’์€ ๋ณต์žกํ•œ ๋””์ง€ํ„ธ ํšŒ๋กœ ์„ค๊ณ„์—์„œ AI ๊ธฐ๋ฐ˜ ๊ฒ€์ฆ ํˆด์„ ๋„์ž…ํ•˜์—ฌ ํ…Œ์ŠคํŠธ์ผ€์ด์Šค ์ž‘์„ฑ ์‹œ๊ฐ„์„ ํš๊ธฐ์ ์œผ๋กœ ์ค„์ž„.
    2๏ธโƒฃ ์ˆ˜๋™์œผ๋กœ ์ฒ˜๋ฆฌํ•˜๊ธฐ ์–ด๋ ค์šด Corner Cases๋ฅผ AI๊ฐ€ ์ž๋™์œผ๋กœ ํƒ์ง€ํ•˜๊ณ  ์ˆ˜์ •ํ•˜์—ฌ, ๊ธฐ๋Šฅ์  Coverage ๋‹ฌ์„ฑ ๊ธฐ๊ฐ„์„ ๋‹จ์ถ•ํ•จ.
    3๏ธโƒฃ Shift-left ์ „๋žต์„ ํ†ตํ•ด ์„ค๊ณ„ ์ดˆ๊ธฐ ๋‹จ๊ณ„์—์„œ ๋ฒ„๊ทธ๋ฅผ ์กฐ๊ธฐ ๋ฐœ๊ฒฌํ•จ์œผ๋กœ์จ ์ฐจ์„ธ๋Œ€ NPU ๋ฐ GPU ํŒน๋ฆฌ์Šค ๊ณต์ •์˜ ์‹œ์žฅ ์ถœ์‹œ ์‹œ์ (Time-to-Market)์„ ์•ž๋‹น๊น€.

๐Ÿ“ข์˜คํ”ˆ์—ฃ์ง€ํ…Œํฌ๋†€๋กœ์ง€, RISC-V ๊ธฐ๋ฐ˜ NPU ๋ฐ ๋ฉ”๋ชจ๋ฆฌ ํ•˜์œ„ ์‹œ์Šคํ…œ IP ๊ณต๊ธ‰ ํ™•๋Œ€

  • โœ”๏ธ๋ฐœํ‘œ ๊ธฐ์—…: OPENEDGES Technology

  • โœ”๏ธ๋ฐœํ‘œ ์ผ์ž: 26.04.24 (IP ๋ผ์ด์„ ์‹ฑ ์—…๋ฐ์ดํŠธ)

  • โœ”๏ธ๋ฐœํ‘œ ๊ธฐ์ˆ  ๋ถ„์•ผ: AI ๊ฐ€์†๊ธฐ(NPU) ๋ฐ ๋ฉ”๋ชจ๋ฆฌ ์ปจํŠธ๋กค๋Ÿฌ IP

  • โœ”๏ธํ•ต์‹ฌ ๋‚ด์šฉ
    1๏ธโƒฃ ๊ตญ๋‚ด IP ์ „๋ฌธ ๊ธฐ์—…์ธ ์˜คํ”ˆ์—ฃ์ง€๊ฐ€ RISC-V ๊ธฐ๋ฐ˜ ํ”„๋กœ์„ธ์„œ์™€ ์ž์‚ฌ์˜ ๊ณ ์„ฑ๋Šฅ NPU๋ฅผ ๊ฒฐํ•ฉํ•œ ํ† ํƒˆ AI ํ”Œ๋žซํผ IP๋ฅผ ๊ธ€๋กœ๋ฒŒ ์‹œ์žฅ์— ๊ณต๊ธ‰ํ•จ.
    2๏ธโƒฃ ํ•˜๋“œ์›จ์–ด ๋ ˆ๋ฒจ์—์„œ NPU์™€ ๋ฉ”๋ชจ๋ฆฌ ์‹œ์Šคํ…œ(NoC, DDR ์ปจํŠธ๋กค๋Ÿฌ)์„ ๊ธด๋ฐ€ํ•˜๊ฒŒ ์ตœ์ ํ™”ํ•˜์—ฌ ์—ฃ์ง€ ๋””๋ฐ”์ด์Šค์—์„œ ์ตœ์ ์˜ TOPS/W(์—๋„ˆ์ง€ ํšจ์œจ์„ฑ) ์„ฑ๋Šฅ์„ ๊ตฌํ˜„ํ•จ.
    3๏ธโƒฃ FPGA ํ”„๋กœํ† ํƒ€์ดํ•‘ ํ™˜๊ฒฝ์„ ์ง€์›ํ•˜์—ฌ ํŒน๋ฆฌ์Šค ๊ณ ๊ฐ์‚ฌ๋“ค์ด ์‹ค๋ฆฌ์ฝ˜ ์ œ์ž‘ ์ „ ๋””์ง€ํ„ธ ํšŒ๋กœ์˜ ์„ฑ๋Šฅ์„ ์ •๋ฐ€ํ•˜๊ฒŒ ๊ฒ€์ฆํ•  ์ˆ˜ ์žˆ๋Š” ์„ค๊ณ„ ์ž์‚ฐ์„ ์ œ๊ณตํ•จ.

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