Compile

compile_ultra의 Default Optimization

• Architectural level or high level synthesis
• Logic level or GTECH
• Gate-level or mapping

Critical Path Re-Synthesis

Logic level과 Gate level을 오가면서 re-synthesis함
CPR is available with the compile command but must be explicitly invoked with the -map_effort high option

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Arithmatic Optimization

DesignWare Library

• A collection of soft IP blocks and Datapath components
• Operator inferencing for arithmetic operators
• Instantiation for a wide variety of standard IP

Operator를 풀어주고, 연산도 최적화 해줌

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Load splitting and logic duplication

large fanout과 critical path가 같이 있을 때,
logic을 복사하여 critial path가 더 좋아지도록 함

Library Analysis (ALIB)

제일 처음 compile_ultra 실행 시
target technology library의 특징(complec Boolean functions)들을
cache(ALIB)로 만듦

• alib_analyze_libs : 명시적으로 ALIB 생성
• alib_library_analysis_path : ALIB가 생성될 UNIX의 위치 지정

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User controllable compile_ultra Optimization

Auto-ungrouping

compile_ultra시 default 로 auto grouping 한다. 이때, sub-design을 잘 안짜르면 달라진다.

A sug-design is considered "poorly partitioned" if all of its data inputs are note directly connected to register outputs, or if all of its adat outputs are not registered.
In other words, a well partitioned sub-design does not have hierarchy boundaries taht "slice" through non-clock combinatorial logic or register inputs.

• compile_ultra -no_autoungroup : disable auto-ungrouping altogether
• set_ungroup <references_or_cells> false : 해당 design이나 cell ungroup 안함

If you want to avoid glue logic at the top level you can disable auto-ungrouping of all top-level cells.
You can use this attribute to maintain the hierarchy of specific designs for verification puposes, or "pipeline" sub-designs for register-retiming purposes.

A file called default.svf is created automatically during compile, which records the "changes" that boundary optimizaiton, register repositioning and ungrouping make to the design.

DesignWare ungrouping

Arithmetic DesignWare component가 compile_ultra시 ungroup 되면서 hierarchy가 사라질 수 있음
→ set_app_var compile_ultra_ungroup_dw false 로 disbale 가능

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Boundary optimization

boundary optimization is ON by default

Boundary optimization propagates constants, unconnected pins, and complement information to reduce delay and/or area.

→ RTL test-bench에 문제가 생길 수 있음
→ If you know in advance which blocks must be preserved for verification purposes, set_boundary_optimization으로 select 된 blocks만 boundary optimization 되도록 설정

• compile_ultra -no_boundary_optimization : disable boundary optimization altogether
• set_boundary_optimization <cells_designs> false : disable boundary optimization on selective sub_designs
• set_app_var compile_enable_constant_propagation_with_no_boundary_opt false
• set_compile_directives -constant_propagation false [get_pins <pin_name>]

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Test-ready synthesis

Scan Register가 있으면 fanout도 추가되고 setup time 등 문제가 생긴다. → dc가 최적화 하려함

set_scan_configuration -style <multiplexed_flip_flop | clocked_scan | lssd | auxclock_lssd>
compile_ultra -scan
compile_ultra -incremental -scan

-style 옵션 에 저 중 하나 사용
처음 compile_ultra 시 -scan 옵션을 주면 그 후에도 계속 줘야함.

Shift-Register 있을 때,
오직 첫번째 register만 대체됨

• set_ap_var compile_seqmap_identify_shift_registers false

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Register replication

• compile_ultra -spg 옵션 사용시 자동적으로 output fanout이 큰 register를 복사함.

Synopsys Physical Guidance (SPG). -spg 옵션 사용을 추천
register replication만 끄고 싶을 때, set_app_var compile_register_replication flase
-spg 말고 register replication만 하고 싶을 때, set_app_var compile_register_replication true

복사했을 때 이름은 _rep#임

• 복사하는 register 갯수를 제한하고 싶을 때
  set_register_replication -num_copies 3 [get_cells Y_reg*] : 갯수를 3개로 하고 싶을 때
  set_register_replication -max_fanout 40 [get_cells Y_reg*] : 최대 fan out 제한

get_attribute [get_cells Y_reg*] register_replication : 복제된 register에 적용된 setting 확인
set_app_var register_replication_naming_style "%s_reg%d" : 이름 스타일 변경
remove_attribute [get_cells Y_reg*] register_replication : 복제된 register에 적용된 세팅 제거

• set_app_var compile_register_replication_across_hierarchy true : 바깥쪽 레지스터 복사

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Adaptive retiming

• compile_ultra -retime 옵션 사용시 WNS 줄이기 위해 retiming 실행

retiming : SoC에서 배운거. 레지스터 왔다갔다.

바뀐 레지스터 이름은 R_##

• set_dont_retime <cells or designs> true : 특정 register나 sub-design retiming 진행 안함

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High-effort timing optimization

• set_app_var compile_timing_high_effort true : default is flase

compile 시간 오래 걸림

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DRC

• set_cost_priority -delay : max_delay를 DRC 보다 우선순위 높게 설정

Priority(descending order)	Notes
min_capacitance	Design rule constraint
max_capacitance	Design rule constraint
max_fanout	Design rule constraint
max_capacitance	Design rule constraint
cell_degradation	Design rule constraint
max_delay	Optimization constraint
min_delay	Optimization constraint
power	Optimization constraint
area	Optimization constraint

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기본적으로 DRC 바꿔도 register clock pin에 바로 연결된 clock net에는 적용 안됨
근데 logic gate 거치는건 적용됨. ← CTS 전에 clock 건드는건 원하는게 아님

Disable DRC buffering in the clock network

1. set_auto_disable_drc_nets -on_clock_network true
• Disable DRC fixing on the entire clock network.
• Does not affect clock nets that are used as data
2. set_dont_touch_network [get_ports ""]
• Applies the "dont_touch" attribute on the entire transitive fanout from the clock ports.
• Does not disable DRC rules
3. set_ideal_network [get_ports ""]
• Applies the "ideal" and the "dont_touch" attributes
• Also disables DRC rules

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User-defined path groups

1. DC는 각 path group 별로 Critical path만 optimize 함
2. group 내의 모든 path가 timing 만족하거나, critical path가 더이상 좋아지지 않을 때 멈춤

group_path -name INPUTS -from [all_inputs]
group_path -name OUTPUTS -to [all_outputs]
group_path -name COMBO -from [all_inputs] -to [all_outputs]

reg-to-reg path는 기본적으로 path 그룹 만들어져 있음
path group defualt : end-point clock object name
report_path_group : path group 확인

내 디자인 바깥과 연결된 path들도 path group으로 설정하여 optimize 진행

group_path -name CLK -critical_range 0.2 : 해당 path group의 critical path 기준 0.2(ns) 범위까지 optimize 진행
Recommendation: Do not excedd 10% of the clock period

group_path -name CLK -critical 0.2 -weight 5 : 가중치 적용
$\sum_{neg\_slack \times weight}$

즉, DC는 해당 path의 Negative Slack 계산할 때 가중치를 곱해서 계산.
Recommendation: 중요한거 5, 덜 중요한거 2, 기본 1

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Pipeline or register retiming

1. compile_ultra -retime 옵션 사용
2. set_optimize_registers true 세팅 적용

code에서 파이프라이닝 하는 법

1. 직접 추가

always @ (posedge clk)
begin
  prodAB <= a * b;
  prodCD <= c * d;
  diffEF <= e - f;
  
  p2_1   <= prodAB + prodCD;
  p2_2   <= diffEF;
  
  y      <= p2_1 + p2_2;
end

2. 한쪽에 몰고 DC가 알아서 추가

data <= a*b + c*d + e-f;

always @ (posedge clk)
begin
  R1 <= data;
  R2 <= R1;
  R3 <= R2;

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Retiming 과정

1. Original RTL Design 에서 Datapath Optimization + Min-period Retiming
2. Min-area Retiming
3. Logic optimization + Adaptive Retiming

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DC에서 하는 법

set_optimize_registers true -design Pipeline
compile_ultra -scan -retime -spg

set_optimize_registers 적용시 auto-ungrouping off 함
파이프라이닝시 자리 바뀐 레지스터 셀 이름은
clockname_r_REG#_S# S는 register stage number

출력 register 건들기 싫을 때
set_dont_retime [get_cells U_Pipeline/P3_reg*] true

• 하나의 design 안에 pipeline을 하려는데 path가 다를 때

1. 각 path별로 디자인 나누고

create_clock -period 1.0 clk
set_optimize_registers true -design "PIPELINE_1 PIPELINE_2 PIPELINE_3"
compile_ultra -spg ...

2. Threshold 사용

create_clock -period 1.0 clk
set_optimize_registers true -design Pipeline -clock clk -delay_threshold 0.97
group_path -name clk -critical_range 0.10
compile_ultra -spg ...

0.97 안되는 애들 파이프라이닝 진행

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Multi-core optimization

• set_host-options -max_corese 8 : DC 돌릴 때 코어 갯수 적용
• report_host_options : 현재 option 확인

Multi-core will require 1 license per 8 cores for:

• DC-Expert
• DC-Ultra
• DesignWare
• DC-Extension
• Power-Compiler
• Test-Compiler

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Disabling runtime-intensive settings

• compile_prefer_runtime : 그냥 빠르게 돌리는거

아래 명령어들에 영향을 끼침

• compile_ultra
• compile_ultra -incr
• optimize_netlist -area

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After compile

1. report_constraint -all_violators
2. report_timing

마지막으로 optimize_netlist -area

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Parallel Command

set_host_options -max_cores 8

update_timing
parallel_execute [list \
  "report_constraint -all > $mylogfile" \
  "report_timing         >> $mylogfile" \
  "report_area           >> $mylogfile" \
  "report_qor            >> $mylogfile"]