Timing Constraints

SungchulCHA·2024년 7월 2일
design compiler

DC

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Clock Delay

Timing Path

  • Startpoint
    • Input port
    • Clock pin of Flip-Flop or register
  • Endpoint
    • Output port
    • D pin (Any input pin of a sequential device, except clock pin)

Create Clock

create_clock -period 2 -name VCLK : virtual clock 생성
create_clock -period 2 [get_ports Clk] : clock object 로 바꿔줌
set_clock_uncertainty -setup T [get_clocks CLK] : T = skew + jitter + margin
set_clock_latency -source -max 3 [get_clocks CLK] : Source Latency 설정
set_clock_latency -max 1 [get_clocks CLK] : Network Latency 설정
set_clock_transition -max T [get_clocks CLK]
set_propagated_clock [get_ports CLK] : CTS 후에

Source Latency : 내 디자인 바깥의 clock latency
Network Latency : 내 디자인 안의 clock latency → CTS 후에는 필요 없음
Clock network delay = Source Latency + Network Latency

Datapath Delay

Input Delay

set_input_delay -max <time> -clock <clock_name> [get_ports <port_name>]

주기 T에서
1. 내 FF의 setup time
2. clock의 uncertainty (= skew + jitter + margin)
3. 바깥의 delay = <time> ← clock이 아니니까 source latency 아님
을 뺀 것이 내 input port 로직에서 사용 가능한 시간

Output Delay

set_output_delay -max <time> -clock <clock_name> [get_ports <port_name>]

주기 T에서
1. clock uncertainty (= skew + jitter + margin)
2. 바깥의 delay = <time> ← 상대 쪽 FF setup time + 상대 로직 시간
을 뺀 것이 내 output port 로직에서 사용 가능한 시간

Time Budgeting

국룰 : clock period의 40%

create_clock -period 10 [get_ports Clk]

set_input_delay -max 6 -clock Clk [all_inputs]
remove_input_delay [get_ports Clk]
set_output_delay -max 6 -clock Clk [all_outputs]

주기가 10이니까 내가 4를 쓰려면 바깥이 6이어야 함

Registered Outputs

내 디자인의 입력 port 로 오는 data가 FF을 나오고,
output port가 FF을 통해 나갈때

set CLK2Q_MAX 1.5
set CLK2Q_MIN 0.9
set ALL_INP_EXC_CLK [remove_from_collection [all_inputs] [get_ports Clk]]

set_input_delay -max $CLK2Q_MAX -clock CLK $ALL_INP_EXC_CLK
set_output_delay -max [expr {10 - $CLK2Q_MIN}] -clock CLK [all_outputs]

10ns 주기에서 FF setup time, hold time이 모두 동일 할 때
input delay, output delay 설정

expr 예시

set PERIOD 10.0; # Returns "10.0"
set FREQ [expr {1 / $PERIOD}]; # Returns "0.1"
echo "Freg = " [expr {$FREQ * 1000}] "MHz"; # Returns "Freq = 100.0MHz"
set_load [expr {[load_of ssc_core_slow/and2a0/A] * 5}] [all_outputs]
# Applies 5 and2a0 gate load to all outputs

Constraints File Recommendations

  1. comment 전엔 semicolon 붙이기
  2. constraint 파일 앞에 reset_design 붙이기
    • 여러 constraint script 적용하면 오직 하나의 스크립트만 reset_design 있어야함
  3. dc.tcl 이나 DESIGN.con 확장자 사용
  4. alias, abbreviating commands(약어) 사용하지 말기

  • Constraints Syntax 체크하는 법
    dcprocheck <constrain_file_name>

  • Port에 걸린 input/output delay 확인하는 법
    report_port -verbose

  • clock constrain 확인하는 법
    report_clock -skew -attr

constraint file 적용 후 check_timing 적용하기

편의성

Redirect

redirect -tee -file <file_name>.rpt {<command>}
ex) redirect -tee -file precompile.rpt {link}
ex) redirect -append -tee -file precompile.rpt {source TOP.con}
ex) redirect -append -tee -file precompile.rpt {report_port -verbose}
ex) redirect -append -tee -file precompile.rpt {report_clock -skew -attr}
ex) redirect -append -tee -file precompile.rpt {check_timing}

help

  • Variables
    printvar *_library
    man target_library

  • Commands
    help *clock
    create_clock -help
    man create_clock
    apropos -symbols_only period

Timing Constraint file Example

# User Var
set Tsetup 0.2; # My register setup time
set Fsetup 0.08; # F6 register setup time

set SKEW 0.03
set JITTER 0.04
set MARGIN 0.05
set UNCERTAINTY [expr {2*$SKEW + $JITTER + $MARGIN}]
set TRANSITION 0.12

set PERIOD 3; # freq = 333.33
set LATENCY_S 0.7; # Source Latency
set LATENCY_N 0.3; # Network Latency

set DATA2S 2.2; # Input port 'data1,2' to input pin of S
set SEL 1.4; # Data arrival time at input port 'sel'

set OUT1 0.42; # Output port 'out1' to D pin of 'F6'
set OUT2 0.81; # Output pin of 'V' to output port 'out2'
set OUT3 0.4; # Setup time of D pin of next Flip-Flop
set COUT 2.45; # Time of input port 'Cin' to output port 'Cout'
#========================================
set lib_name cb13fs120_tsmc_max
current_design MY_DESIGN

# Reset all constraints
reset_design

# Create Clock and setting
create_clock -period $PERIOD [get_ports clk]
set_clock_latency -source -max $LATENCY_S [get_clocks clk]
set_clock_latency -max $LATENCY_N [get_clocks clk]

set_clock_uncertainty -setup $UNCERTAINTY [get_clocks clk]
set_clock_transition $TRANSITION [get_clocks clk]

# Input Delay
set_input_delay -max [expr {$PERIOD - $Tsetup - $UNCERTAINTY - $DATA2S}] -clock clk [get_ports data*]
set_input_delay -max [expr {$SEL - $LATENCY_S - $LATENCY_N}] -clock clk [get_ports sel] 

# Output Delay
set_output_delay -max [expr {$OUT1 + $Fsetup}] -clock clk [get_ports out1*]
set_output_delay -max [expr {$PERIOD - $UNCERTAINTY - $OUT2}] -clock clk [get_ports out2*]
set_output_delay -max $OUT3 -clock clk [get_ports out3*]

# Combo and Virtual clock
set_input_delay -max 0.1 -clock clk [get_ports Cin*]; # 3(Period) - 2.45(Combo logic) - 0.15(Uncertainty) = 0.4
set_output_delay -max 0.3 -clock clk [get_ports Cout*]

Capacitance

Capacitive load에 따라 transition 속도가 변함

명령어 사용법

Output Capacitive Load

  1. set_load -max [expr {30.0/1000}] [get_ports B]
  2. set_load -max [load_of my_lib/AN2/A] [get_ports B]
    set_load -max [expr {[load_of my_lib/inv1a0/A] * 3}] [get_ports B]

Input Transition Time

  1. set_input_transition -max 0.12 [get_ports A]
  2. set_driving_cell -max -lib_cell OR3B [get_ports A]
    set_driving_cell -max -lib_cell FD1 -pin Qn [get_ports A]

Load Budgeting

Assumptions:
1. 모든 블럭의 input port의 maximum fanout capacitance limit이 "and2a1" 10개 짜리다.
2. Output ports는 최대 3개의 block을 가질 수 있다.
3. output 의 driving gate는 inv1a1이다.

set ALL_INP_EXC_CLK [remove_from_collection [all_inputs] [get_ports Clk]]

# Assume a weak driving buffer on the inputs
set_driving_cell -max -no_design_rule -lib_cell inv1a1 $ALL_INP_EXC_CLK; # 들어오는 거

# Limit the input load
set MAX_INPUT_LOAD [expr {[load_of ssc_core_slow/and2a1/A] * 10}]
set_max_capacitance $MAX_INPUT_LOAD $ALL_INP_EXC_CLK; # 내 디자인 안에서

# Assuming outputs will only be tied to 3 subsequent blocks
set_load -max [expr {$MAX_INPUT_LOAD * 3]} [all_outputs]; # 나가는 거

-no_design_rule
DC는 design rule 중 가장 제한적인 조건을 적용하기에,
driving cell 값이 사용자가 정의한 AND2 10개보다 작으면
set_max_capacitance를 무시함. 이를 방지하는 옵션

set_max_capacitance : DRC command. port의 fanout의 capacitance를 제한함

다른 방법

set MAX_CAP 0
set OUTPUT_PINS [get_lib_pins $LIB_NAME/*/* -filter "direction == 2"]
foreach_in_collection pin $OUTPUT_PINS {
   set NEW_CAP [get_attribute $pin max_capacitance]
   if {$NEW_CAP > $MAX_CAP} {
      set MAX_CAP $NEW_CAP    }
   }
set_load -max $MAX_CAP [all_outputs]

Example

# Timing constraints go here

set_max_capacitance $MAX_INPUT_LOAD $ALL_INP_EXC_CLK
set_load -max [expr {$MAX_INPUT_LOAD * 3}] [all_outputs]
set_load -max 0.080 [get_ports OUT23]
set_load -max [load_of slow_proc/NAND2_3/A] [get_ports OUT42]
set_input_transition -max 0.12 [remove_from_collection [all_inputs] [get_ports B]]
set_driving_cell -max -lib_cell FD1 -pin Q [get_ports B]

# Algorithm to find largest max_capacitnace in library and apply that value as a output load
set LIB_NAME ssc_core_slow
set MAX_CAP 0
set OUTPUT_PINS [get_lib_pins $LIB_NAME/*/* -filter "direction == 2"]
foreach_in_collection pin $OUTPUT_PINS {
   set NEW_CAP [get_attribute $pin max_capacitance]
   if {$NEW_CAP > $MAX_CAP} {
      set MAX_CAP $NEW_CAP    }
   }
set_load -max $MAX_CAP [all_outputs]

Load Constraint file Example

# User Timing Var
...
#========================================
set lib_name cb13fs120_tsmc_max
current_design MY_DESIGN

# Reset all constraints
reset_design

# Create Clock and setting
...

# Input Delay
...

# Output Delay
...

# Combo Logic Delay
...

#=======================================================
# User Cap Var
set DATA_D_CELL bufbd1
set CIN_TRANSITION 0.12

set OUT_L [expr {2 * [load_of $lib_name/bufbd7/I]}]
set COUT [expr {25.0/1000}]
#=======================================================
# Input Drivers
set_driving_cell -lib_cell $DATA_D_CELL -library $lib_name\
 [remove_from_collection [all_inputs] [get_ports "clk Cin*"]]

set_input_transition $CIN_TRANSITION [get_ports Cin*]

# Output Loads
set_load -max $OUT_L [get_ports out*]
set_load -max $COUT [get_ports Cout*]
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SungchulCHA
Myongji UNIV. B.S. in Electronic Engineering
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