Timing Analysis

report_timing

• Incr : Individual Contribution to Path Delay(Net + Cell Delay)
• Path : Running Total of the Path Delay

report_timing Options

• -delay <max/min>
• -to <pin | port | clock | list>
• -from <pin | port | clock | list>
• -through <pin | port | list>
• -group
• -input_pins : cell delay, net delay 구분
• -max_paths <path_count> : 총 몇 개의 path를 출력할 건지. defualt : nworst
• -nworst <paths_per_endpoint_count> : End point 당 몇 개의 path를 볼 건지. defualt : 1
• -nets
• -capacitance
• -significant_digits <number> : 유효 숫자
• -all_violators : violated 난 path 다 보여줌

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Constraint Options

create_clock

1. create_clock -period 2 [get_ports Clk]
2. create_clock -period 2 -name My_Clk [get_ports Clk]

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3. create_clock -period 2 -waveform {0 0.6} -name My_Clk [get_ports Clk]

   -waveform {rising edge falling edge}
   waveform 옵션으로 latency 주는 짓은 하지 말자!!!

usage

create_clock -period 4 -waveform {0 3} -name REFRESH_CLK [get_ports Clk_1]
set_clock_latency -max 2 [get_clocks REFRESH_CLK]

Falling Clock Edge

set_input_delay -max 0.3 -clock Clk -clock_fall [get_ports A]

Usage

create_clock -period 3.6 -waveform {0.0 1.2} [get_ports Clk]
set_input_delay -max 1.3 -clock Clk -clock_fall [get_ports A]

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Multiple Input Paths

create_clock -period 2 [get_ports Clk]
set_input_delay -max 0.3 -clock Clk -clock_fall [get_ports A]
set_input_delay -max 1.2 -clock Clk -add_delay [get_ports A]

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Driving Cell

set_input_delay -max 0.6 -clock Clk [get_ports A]
set_driving_cell -max -lib_cell NAND2_3 [get_ports A]

input delay 시간 이후로 transition 시작
transition 속도는 driving cell 설정에 따라 바뀜
즉, 두 가지가 데이터 도착 시간에 영향

External Capacitive Load on Inputs

create_clock -period 2 [get_ports Clk]
set_input_delay -max 0.6 -clock Clk [get_ports A]
set_output_delay -max 0.8 -clock Clk [get_ports B]
set_load -max 0.030 [get_ports OUTPUT_B]

set_driving_cell -max -lib_cell NAND2_3 [get_ports INPUT_A]
set_load -max 0.012 [get_ports INPUT_A]

INPUT_A로 들어올 때 내 디지인 말고 다른 디자인으로 들어갈 때
set_load를 input에 적어서 명시함

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Complex Output Paths

create_clock -period 4 [get_ports Clk]
set_output_delay -max 2.5 -clock Clk [get_ports B]
set_output_delay -max 0.7 -clock Clk -add_delay -clock_fall [get_ports B]

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CTS 영향

Pre-CTS: Ideal Clock Latencies

create_clock -p 4 -n CLK [get_ports CLOCK]
set_clock_latency -max 1.0 [get_clocks CLK]

set_input_delay -clock CLK -max 2.2 [get_ports In1]

Post-CTS: Propagated Clock Sources

create_clock -p 4 -n CLK [get_ports CLOCK]
set_clock_latency -max 1.0 [get_clocks CLK]
set_propagated_clock [all_clocks]

set_input_delay -clock CLK -max 2.2 [get_ports In1]

set_propagated_clock 을 사용하면 clock_latency 사라짐
즉, 내 디자인 바깥의 clock latency 사라져서 0이 됨

Solution 1

create_clock -p 4 -n CLK [get_ports CLOCK]
set_clock_latency -max 1.0 [get_clocks CLK]

create_clock -period 4 -name V_CLK
set_clock_latency -max 1.0 [get_clocks V_CLK]

set_input_delay -clock V_CLK -max 2.2 [get_ports IN1]

Solution 2

clock 말고 data path에 delay 주기

create_clock -p 4 -n CLK [get_ports CLOCK]
set_clock_latency -max 1.0 [get_clocks CLK]

set_input_delay -clock CLK -max 3.2 -network_latency_included [get_ports IN1]

"absolute" arrival time of data at input port IN1
이 delay(2.2) 에다가 기존 latency(1.0) 추가되서 느려진다 생각

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Output Delay with Network Latency

• pre-cts output delay

create_clock -p 4 -n CLK [get_ports CLOCK]
set_clock_latency -max 1.0 [get_clocks CLK]

set_output_delay -clock CLK -max 2.5 [get_ports B]

• post-cts output delay

create_clock -p 4 -n CLK [get_ports CLOCK]
set_clock_latency -max 1.0 [get_clocks CLK]

set_output_delay -clock CLK -max 1.5 -network_latency_included [get_ports B]

주기(4)에서
기존 output delay(2.5)를 빼기

Output Delay with Source Latency

create_clock -p 4 -n CLK [get_ports CLOCK]
set_clock_latency -source -max 0.4 [get_clocks CLK]
set_clock_latency -max 1.0 [get_clocks CLK]

set_output_delay -clock CLK -max 1.1 \
                 -source_latency_included \
                 -network_latency_included [get_ports B]

주기(4)에서
해당 FF의 clock의 source latency(0.4) 만큼 빼고
기존 outputt delay(2.5)를 빼기

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다 섞어서

• pre-cts

create_clock -period 2 [get_ports Clk]
set_clock_latency -source -max 0.3 [get_clocks Clk]
set_clock_latency -max 0.12 [get_clocks Clk]

set_input_delay -max 0.6 -clock Clk [all_inputs]
set_output_delay -max 0.8 -clock Clk [all_outputs]

Solution 1 : Virtual Clock

create_clock -period 2 [get_ports Clk]
create_clock -period 2 -name Clk_Jane
create_clock -period 2 -name Clk_Joe

set_clock_latency -source -max 0.30 [get_clocks Clk]
set_clock_latency -source -max 0.18 [get_clocks Clk_Jane]
set_clock_latency -source -max 0.30 [get_clocks Clk_Joe]

set_clock_latency -max 0.12 [get_clocks Clk]
set_clock_latency -max 0.12 [get_clocks Clk_Jane]
set_clock_latency -max 0.07 [get_clocks Clk_Joe]

set_input_delay -max 0.6 -clock Clk_Jane [all_inputs]
set_output_delay -max 0.8 -clock Clk_Joe [all_outputs]

Solution 2 : Included

create_clock -period 2 [get_ports Clk]
set_clock_latency -source -max 0.3 [get_clocks Clk]
set_clock_latency -max 0.12 [get_clocks Clk]

set_input_delay -max [expr {0.6 + 0.18 + 0.12}] -clock Clk \
  -source_latency_included -network_latency_included [all_inputs]
set_output_delay -max [expr {0.8 - (0.30 + 0.07}] -clock Clk \
  -source_latency_included -network_latency_included [all_outputs]