Design Compiler Objects

SungchulCHA·2024년 7월 2일

DC

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Design Objects

  • Verilog 입장
    port(=clock), pin, net, cell이 있음.

  • Schematic 입장
    port, clock, cell, net, design, pin이 있음.

Ports versus Pins

  • 'Ports' are the inputs and outputs of the current design
  • 'Pins' are the inputs and outputs of any cell that is instantiated in the current design

→ 현재 디자인에 따라 Port가 Pin이 될 수도 있음

get_* Commands

  • get_nets : current design의 net들. -hier로 sub-block도 가능
  • get_pins <cell/pin> : cell들의 input/output pins. -hier로 sub-block 가능
  • get_ports : current design의 input/output/bidir ports. -hier 가능
  • get_cells : cells(instances) in the current design. -hier 로 sub-blocks도 가능
  • get_clocks : current design이나 above design에서 정의된 clock object
  • get_designs : DC memory에 있는 designs
  • get_libs : DC memory에 있는 libraries
  • get_lib_cells <libname/cellname> : library 안에 있는 cell들
  • get_lib_pins <libname/cellname/pinname> : library 안에 있는 cell의 pin들

all_* Commands

arguments 없음

  • all_inputs : current design의 모든 input, inout ports
  • all_outputs : current design의 모든 output, inout ports
  • all_clocks : current design과 below에서 정의된 clock들
  • all_registers : 현재 디자인의 register cell들의 hierarchy
  • all_ideal_nets
  • all_fanin
  • all_fanout
  • all_connected
  • all_dont_touch
  • all_high_fanout

그 외

  • query_objects : 정보 보기
  • sizeof_collection : 개수
  • filter_collection [get_cells *] "ref_name =~ AN*" : 해당 조건에 만족하는 것들만
  • get_cells * -filter "dont_touch == true : 해당 조건에 만족하는 것들만
  • list_attributes -application -class <object_type> : attribute 확인

모르겠는거 man으로 찾아보기

활용

set_driving_cell 5 [remove_from_collection [all_inputs] [get_ports CLK]]
set fastclks [get_clocks * -filter "period < 10"]
get_cells -hier -filter "is_unmapped != true"
foreach_in_collection cell [get_cells -hier * -filter "is_heirarchical == true"] {echo "Instance [get_object_name $cell] is hierarchical"}


Objects and Attributes

Object 종류
design, port, pin, cell, net, clock, lib, reference, cluster, bag

  • Ports' attributes
    direction, driving_cell_rise, load, max_capacitance, ...
  • Cells' attributes
    dont_touch, is_hierarchical, is_mapped, is_sequential, ...

Collection과 list

  • Tcl lists are structures to store user-defined data
  • Collections are used to access database data

collection을 반환하는 commands들은 list용 명령어 안됨

  • add_to_collection : Add object(s)
  • compare_collections : compares two collections
  • copy_collection : Make a copy of collection
  • filter_collection : Filter a collection, resulting in a new collection
  • foreach_in_collection : Iterate over a collection
  • index_collection : Extract object from collection
  • remove_from_collection : Remove object(s) from a collection
  • sizeof_collection : Number of objects in a collection
  • sort_collection : Create a sorted copy of a collection
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Myongji UNIV. B.S. in Electronic Engineering

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