Design Compiler 시작하기

SungchulCHA·2024년 7월 1일

DC

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Loading Logical Libraries

dc_shell -topo 실행 및 design read

UNIX% dc_shell -topo : dc를 topographical 로 실행 ← license 필요
dc_shell-topo> read_verilog <file_name>.v : verilog 파일의 Design 불러오기

library가 link 제대로 안되어도 read는 상관없음
current design 바꿔주는 법 : current_design <design_name>

Constraining and Compiling

dc_shell-topo> source <constrain_file_name>.con : Constrain file 적용
compile_ultra : compile

compile 보다 compile_ultra가 더 좋은거
LICENSE 구매해야함
compile_ultra에서 library가 제대로 링크되어 있지 않으면 Error 발생
대부분의 Logicla Technology Library는 .db 즉, binary 파일로 되어있음

printvar target_library : 현재 dc의 target library file 보는 법
get_app_var target_library : 현재 dc의 target library file 보는 법
get_app_var -list -only_changed_vars * : 바뀐 app variable 출력
set_app_var target_library <library_file_name>.db : 새로운 target library file 적용

Saving

dc_shell-topo> write_file -format verilog -output <file_name>.v : 저장하는법
현재 design만 저장됨(compile 이전이라면 rtl, compile 이후라면 netlist임)

`link_library` 적용법

set_app_var link_library "* $target_library"

* : dc의 memory 즉 읽었던 library들, search_path에 선언된 경로들

link library를 변경 후에는
link 명령어 적용해야함

dc_shell-topo> read_verilog mapped/MYREG_mapped.v
dc_shell-topo> set_app_var target_library libs/20nm_wc.db
dc_shell-topo> set_app_var llink_library "* $target_library"
dc_shell-topo> link
dc_shell-topo> source cons/myreg.con
dc_shell-topo> check_timing
dc_shell-topo> report_constraint -all
...

link 이후에 반환값이 1이면 성공, 0이면 fail

Switching Technology Libraries

set_app_var target_library libs/new_20nm_wc.db
set_app_var link_library "* libs/new_20nm_wc.db"
read_verilog ORIGINAL_RTL.v
link
source cons/new.con
check_timing
compile_ultra

netlist만 있을 때

set_app_var search_path "$search_path libs cons"
set_app_var target_library libs/new_20nm_wc.db
set_app_var link_library "* libs/old_40nm_wc.db"
read_verilog OLD_NETL.v
link
source cons/new.con
check_timing
compile_ultra -incremental
write_file -f veirlog -out NEW_NTL.v
set_ap_var link_library "* $target_library"

-incremental : runs faster and is suitable whenever a mapped design netlist is available as a starting point

`search_path` 적용법

set_app_var search_path "$search_path <path_dir>"

search_path는 왼쪽에서 오른쪽으로 읽어들임
즉, 왼쪽에 있던 dir에서 찾으면 해당 cell(?)이 우선 적용

.synopsys_dc.setup

적용 순서
1. $SYNOPSYS/admin/setup/.synopsys_dc.setup : synopsys 설치 위치
2. ~user/.synopsys_dc.setup : 사용자 setup 위치(home 디렉토리)
3. ./.synopsys_dc.setup : dc 실행 위치

적용 우선순위
1. design compiler 실행 위치의 setup 파일
2. 사용자 home 디렉토리의 setup 파일
3. synopsys 설치 경로의 setup 파일

Loading Hierarchical RTL Design

`read_verilog`

파일이 여러개로 나뉘어져 있을때,
read_verilog {TOP.v A.v B.v} : Current design is 'MY_TOP' ← 젤 먼저 부른거
하나의 파일 안에 여러 module이 선언되어 있을 때,
read_verilog TOP_hier.v : Current design is 'MY_A' ← 젤 위에 선언된 모듈

link 하기 전에 current_design 명령어로 현재 design 확인하기

link 이후에 check_design으로 error 확인하기

`analyze` & `elaborate`

set_app_var search_path "$search_path rtl unmppd mppd"
analyze -format verilog {A.v B.v C.v TOP.v}
elaborate MY_TOP

current_design <design_name> 으로 바꿀 필요 없음
analyze는 호출 순서 상관 없음
elaborate MY_TOP -parameters "A_WIDTH=8, B_WIDTH=16" : parameter 설정

`read_ddc`

.ddc : design compiler data file

만약 TOP.v 안에 선언된 모듈이 .ddc 파일로 저장되어 있다면,

set_app_var search_path "$search_path ../JOE/unmapped"
set_app_var link_library "* $target_library IP.db"
read_verilog {A.v B.v TOP.v}
read_ddc {decode.ddc ENCODE.ddc}
current_design MY_TOP
link

module 내에 instantiation 된 이름과 ddc 파일의 이름이 달라도 가능은 함 : Auto-loading
하지만 비추
file name must be <design_name.ddc>

Saving

Before compile

read_verilog {A.v B.v TOP.v}
current_design MY_TOP
link
check_design
write_file -f ddc -hier -output unmapped/MY_TOP.ddc
source TOP.con
check_timing
compile_ultra

After compile

read_verilog {A.v B.v TOP.v}
current_design MY_TOP
link
check_design
write_file -f ddc -hier -output unmapped/MY_TOP.ddc
source TOP.con
check_timing
compile_ultra
change_names -rule verilog -hier
write_file -f verilog -hier -output mapped/MY_TOP_ntl.v
write_file -f ddc -hier -output mapped/MY_TOP.ddc
write_icc2_files -out mapped/MY_TOP_icc2

Loading Physical Data

DC에서 이 내용들이 필요한가...?

From the ASIC Vendor
- Reference libraries ← Cell size and pin locations
  - Standard cells
  - IP or macro cells
  - I/O pad cells
- Technology data
  - Technology File ← layout DRC rules, vias, routing layers
  - TLUPlus files ← Parasitic net RC
  - Layer Mapping File ← Look up table 같은거
From the layout team
- Floorplan information ← Constrains placement of std cells and macros
Created by DC during setup
- Design library ← "Container" to hold the physical design and technology data

Technology File (`.tf` file)

metal이랑 via 정보, 단위들 있음

TLUPlus files

C랑 R look-up table 있음

Layer Mapping File

TLUPlus file의 layer/via name이랑 technology file의 layer/via name mapping 해줌

Loading Physical Technology Data

첫 실행

set_app_var mw_reference_library "./mw_libs/sc ./mw_libs/macros"
set_app_var mw_design_library ./ORCA_design_lib

create_mw_lib \
  -technology           ./mw_libs/tech/20nm.tf \
  -mw_reference_library $mw_reference_library \
                        $mw_design_library

open_mw_lib ./ORCA_design_lib
check_library

set_tlu_plus_files \
  -max_tluplus  ./mw_libs/tlup/20nm_max.tluplus \
  -tech2itf_map ./mw_libs/tlup/20nm.map
check_tlu_plus_files

re-load

open_mw_lib $mw_design_library

set_tlu_plus_files \
  -max_tluplus  ./mw_libs/tlup/20nm_max.tluplus \
  -tech2itf_map ./mw_libs/tlup/20nm.map

Core 만들기

이걸 왜 DC에서 하는거지...?

set_utilization 0.6 : 가용성 설정
set_aspect_ratio 0.5 : 가로 세로 비율 설정. height이 width의 0.5배됨
set_placement_area -coordinate {0 0 600 400} : (0, 0) 에서 (600, 400)
set_port_side {R} Port_N : right side에 Port_N 만듦. (left : L, top : T, bottom : B)

set_cell_location -coordinate {400 160} -fixed -orientation {N} RAM1 : (400, 160)에서 부터 RAM1 이름의 cell 만듦

create_placement_blockage -name Blockage1 -coordinate {350 110 600 400} : (350, 100)에서 (600, 400) 중 cell 빼고 blockage 만듦

set_port_location -coordinate {0 40} PortA : (0, 40)에 PortA 만듦

report_physical_constraints

DC-T 에서 지원하는 것들

Core Area
- Relative Constraints
  - set_aspect_ratio
  - set_utilization
- Exact Constraints
  - set_placement_area
  - create_die_area
Ports
- Relative Constraint
  - set_port_side
- Exact Constraint
  - set_port_location
Macros
- Exact Constraint
  - set_cell_location
Placement and Routing Guidance
- Exact Constraints
  - create_placement_blockage
  - create_bounds
  - create_site_row
  - create_voltage_area
  - create_net_shape
  - create_wiring_keepouts

Second Synthesis After Floorplan

DEF 에 floorplan data가 있으면

extract_physical_constraints MYDESIGN.def
read_floorplan MYDESIGN_suppl_fp.tcl

Tcl에 floorplan data가 있으면

read_floorplan MYDESIGN_fp.tcl
read_floorplan MYDESIGN_suppl_fp.tcl
read_floorplan MYDESIGN_fp.objects

MYDESIGN.def : Primary FP data
MYDESIGN_suppl_fp.tcl : Supplement FP data
MYDESIGN_fp.objects : Physical-only cells

Setup Files

.synopsys_dc.setup 에서
source common_setup.tcl,
source dc_setup.tcl
하고

common_setup.tcl 수정

Example

UNIX% cd risc_design
UNIX% dc_shell -topo

dc_shell-topo> set_app_var mw_reference_library $MW_REF_LIBS
dc_shell-topo> set_app_var mw_design_library $MW_DESIGN_LIB
dc_shell-topo> create_mw_lib -technology $TECH_FILE \
                             -mw_reference_library $mw_reference_library \
                                                   $mw_design_library
dc_shell-topo> open_mw_lib $mw_design_library
dc_shell-topo> check_library
dc_shell-topo> set_tlu_plus_files -max_tluplus $TLU_MAX_FILE \
                                  -tech2itf_map $MAP_FILE
dc_shell-topo> check_tlu_plus_files
dc_shell-topo> define_design_lib WORK -path ./work
dc_shell-topo> read_verilog {A.v B.v TOP.v}
dc_shell-topo> current_design TOP
dc_shell-topo> link

#If some physical constraints are known before first compile
dc_shell-topo> source MYDESIGN_phys_cons.tcl
# Once an actual floorplan is available
dc_shell-topo> read_floorplan MYDESIGN.fp
# 필요하면
dc_shell-topo> extract_physical_constraints MYDESIGN.def

dc_shell-topo> source timing.cons
dc_shell-topo> check_design
dc_shell-topo> write_file -f ddc -hier -out unmpd/TOP.ddc
dc_shell-topo> source -echo -verbose TOP.con
dc_shell-topo> check_timing
dc_shell-topo> compile_ultra
dc_shell-topo> report_constraaint -all_violators
dc_shell-topo> change_names -rule verilog -hier
dc_shell-topo> write_file -f verilog -hier -out mpd/TOP.v
dc_shell-topo> write_file -f ddc -hier -out mpd/TOP.ddc
dc_shell-topo> write_icc2_files -output mpd/TOP/icc2

SungchulCHA

Myongji UNIV. B.S. in Electronic Engineering

이전 포스트

Introduction to Design Compiler

다음 포스트

Design Compiler 시작하기

DC

Loading Logical Libraries

dc_shell -topo 실행 및 design read

Constraining and Compiling

Saving

`link_library` 적용법

Switching Technology Libraries

`search_path` 적용법

.synopsys_dc.setup

Loading Hierarchical RTL Design

`read_verilog`

`analyze` & `elaborate`

`read_ddc`

Saving

Loading Physical Data

Technology File (`.tf` file)

TLUPlus files

Layer Mapping File

Loading Physical Technology Data

Core 만들기

DC-T 에서 지원하는 것들

Second Synthesis After Floorplan

Setup Files

Example

Introduction to Design Compiler

Design Compiler Objects

0개의 댓글

Design Compiler 시작하기

DC

Loading Logical Libraries

dc_shell -topo 실행 및 design read

Constraining and Compiling

Saving

link_library 적용법

Switching Technology Libraries

search_path 적용법

.synopsys_dc.setup

Loading Hierarchical RTL Design

read_verilog

analyze & elaborate

read_ddc

Saving

Loading Physical Data

Technology File (.tf file)

TLUPlus files

Layer Mapping File

Loading Physical Technology Data

Core 만들기

DC-T 에서 지원하는 것들

Second Synthesis After Floorplan

Setup Files

Example

Introduction to Design Compiler

Design Compiler Objects

0개의 댓글

`link_library` 적용법

`search_path` 적용법

`read_verilog`

`analyze` & `elaborate`

`read_ddc`

Technology File (`.tf` file)