Efficient Synthesis Coding Style Techniques

Unnecessary always Statements

// Reg_0 conditionally assigned
always @ (posedge Clock)
begin

  if (Sel == 2'b00)
    begin
      Reg_0 <= Data_In_A + Data_In_B;
    end
    
end

// Reg_1 conditionally assigned
always @ (posedge Clock)
begin

  if (Sel == 2'b01)
    begin
      Reg_1 <= Data_In_A - Data_In_B;
    end
    
end

...

// Reg_3 ocndiionally assigned
always @ (posedge Clock)
begin

  if (Sel == 2'b11)
    begin
      Reg_3 <= Data_In_A + (~ Data_In_B);
    end
    
end

// conditionallly select Reg_N
assign Data-Out = 
    (Sel == 2'b00) ? Reg_0 :
    (Sel == 2'b01) ? Reg_1 :
    (Sel == 2'b10) ? Reg_2 : Reg_3;