Mismatch

Incomplete Event List Mismatch

• Original Verilog code

always @ (A, B)
  begin
    D = (A & B) | C;
  end

• Post-syntehsis simulation

always @ (A, B, C)
  begin
    D = (A & B) | C;
  end

Synthesis 툴이 강제적으로 추가한다.

• Blocking, Nonblocking

always @ (In_A, In_B)
begin
  Intermediate_Variable = In_A & In_B;
  Data_Out = Intermediate_Variable;
end

Blocking assignment to Intermediate_Variable occurs immediately.
read after it is updated.

always @ (In_A, In_B, Intermediate_Variable)
begin
  Intermediate_Variable <= In_A & In_B;
  Data_Out = Intermediate_Variable;
end

Nonblocking assignment to Intermediate_Variable is scheduled to occur at the end of the current Verilog simulation cycle.
read before it is updated.
Intermediate_Variable MUST be in the event list.

one_hot Directive

// synopsys one_hot "Set, Reset"
always @ (posedge Clock, posedge Treset, posedge Set)
begin

  if (Set)
    begin
      Data_Out <= 1'b1;
    end
  else if (Reset)
    begin
      Data_Out <= 1'b0;
    end
  else
    begin
      Data_out <= Data_In;
    end
end

Set과 Reset 이 동시에 1이되는 경우 문제, Mismatch가 발생

`ifndef SYNTHESIS

  always @ (Reset, Set)
  begin
  
    if (Reset & Set)
      begin
        $display ("one_hot violation for Reset and Set");
      end
    
  end
`endif

해당 구문으로 Simulation에서 Violation Check 할 수 있도록 추가하기

Subprogram Variables

task Task_Mismatch (input  T_In_A,
                    input  T_Sel,
                    output T_Out
  reg Internal_Reg;
  
  begin
  
    if (T_Sel)
      begin
        Internal_Reg = T_In_A;
      end
    
    T_Out = Internal_Reg;
    
  end
  
endtask

Task_Mismatch(Data_In, Enable, D_Out)

Latch 생성을 원했지만, 합성하면 D_Out = Enable & Data_In 의 AND Gate가 나옴

• 해결책
  hdlin_infer_function_local_latches 를 true로 바꾸면 subprograms 가 latch로 생성된다.

Equality Check

input  [7:0] Data_A;
input  [7:0] Data_B;
output [7:0] Data_C;
reg    [7:0] Data_C;

always @ (Data_A, Data_B)
begin

  if (Data_A == Data_B)
    begin
      Data_C = Data_A;
    end
    
end

simulation 상에서는 문제 없는데 실제 회로에서는 비교기와 결과 실행에 시간이 필요하다.

input Clock;
input  [7:0] Data_A;
input  [7:0] Data_B;
output [7:0] Data_C;
reg    [7:0] Data_C;

always @ (posedge Clock)
begin

  if (Data_A == Data_B)
    begin
      Data_C = Data_A;
    end
    
end

FF으로 설계하기

Extension

input [1:0] Sel_X;
input [1:0] Sel_Y;

case (Sel_X ~^ Sel_Y)

  3'b000:  Data_Out = In_A + In_B;
  3'b001:  Data_Out = In_C + In_D;
  3'b010:  Data_Out = In_E + In_F;
  3'b011:  Data_Out = In_G + In_H;
  default: Data_Out = In_I + In_J;
  
endcase

• Option #1

  • Compute the operands in two bits, then zero extend the result to three bits
  • Leftmost bit of the case expression is now 1'b0 so, the default branch will NEVER be executed

• Option #2

  • Zero extend the two bit operands to three bits and then excute the ~^ operator on these three bit operands
  • Leftmost bit of the case expression is no 1'b1 so, the default branch will ALWAYS be executed

Synopsys VCS, Synthesis는 Option #1