Floor Planning

SungchulCHA·2024년 2월 13일
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ICC2

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1. chip 만들기

Create the Initial Floorplan

synopsys에서 기본 제공

  • Rectangular
  • L-shape
  • T-shape
  • U-shape

좌표 찍어 만들기

initialize_floorplay -control_type core \
    -boundary { {0.0 0.0} {800.0 0.0} {800.0 200.0} {1013.08 200.0} 
    {1013.08 780.8240} {416.4800 780.8240} {416.48 596.904} {0.0 596.904} } \
    -...

VA Creation

set_shaping_options -guard_band_size 10 : VA 다른 부분 마진

create_voltage_area -power_domains <PD_RISC_CORE> \
    -region {...} \
    -guard_band ...

set_voltage_area PD_RISC_CORE -is_fixed
  • To reset the is_fixed attribute
set_attribute -objects [get_voltage_areas <PD_RIISC_CORE>] \
    -name is_fixed \
    -value false

2. Place Macros and Standard Cells

Macro Placement

create_placement -floorplan [-congestion ...] : 그냥 미리 해보는거, 옵션 넣어줄 수 있음

  • configuration application options
    plan.place.*, plan.macro.*, plan.macro.auto_macro_array*

Fixing Macro Placement

  • set_macro_constraints
  • set_macro_relative_location
  • create_macro_array
  • create_macro_relative_location_placement

마지막에

  • set_app_options -list \ { place.coarse.fix_hard_macros true }

3. Place I/O Pins

set_block_pin_constraints -self -allowed_layers "M3 M4" \
    -sides "1 2 3 4 5" | -exclude_sides "7 8"
set_individual_pin_constraints -ports ... -

place_pins -self

4. Global Route Congestion

route_global -floorplan true -congestion_map_only true : overflow 확인

해결법

  1. keepout margin
    create_keepout_margin -type hard -outer {15 0 18 0} RAM5

  2. blockage
    create_placement_blockage -boundary {{345 355} {392 400}} -name LL_CORNER -type <hard | soft>

다시 floor plan

create_placement -floorplan [-incremental]
route_global -floorplan true -congestion_map_only true

-incremental : 문제 생긴 부분만 다시 floorplan

5. Power Planning

6. Write DEF

power planning 끝났으면 def 파일 떠서 PI에 갖다줌

write_def \
    -include {rows_tracks cells ports specialnets vias{ \
    -objects [add_to_collection $all_macro_cells \
                [get_cells -hierarchical -filter is_physical_only]]
    ORCA_TOP.def
    
write_floorplan -format icc -output ORCA_TOP.fp \
    -include {voltage_areas blockages bounds route_guides}

physical only cell : filler cell, tie cell 같은 cell들
top이 써야 하는 명령어

profile
Myongji UNIV. B.S. in Electronic Engineering

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