Timing Setup

SungchulCHA·2024년 2월 8일
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ICC2

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MCMM : 시나리오 여러개

  • Scenario = Mode + Corner
  • modes = .sdc : test mode, low power mode 등등
  • corners = PVT : .lib 안에 있음

Mode, Corner and Scenario Setup

read_sdc C1_corner.sdc
read_sdc M1_mode.sdc
read_sdc M2_mode.sdc

create_mode M1
craete_mode M2

create_corner C1

create_scenario -mode M1 -corner C1 -name M1_C1
create_scenario -mode M2 -corner C1 -name M2_C1

하지만 실제로는 sdc 파일 1개, 많아봐야 2개만 사용

Check Timing Constraints

check_timing
foreach_in_collection mode [all_modes] {
    current_mode $mode
    report_exception
    report_case_analysis
    report_disable_timing
}

Scenario Examples

create_scenario -mode mFUNC -corner cSLOW
create_scenario -mode mTEST -corner cSLOW
create_scenario -mode mFUNC -corner cFAST
create_scenario -mode mTEST -corner cFAST

# Disable setup timing analysis and optimization for the FAST corner scenarios
# Disable leakage power analysis and optimization for the TEST mode scenarios
set_scenario_status *cFAST -setup false
set_scenario_status mTEST* -leakage_power false

place_opt

# For post-route analysis activate all scenarios and enable all analyses
set_scenario_status * -active true -all

# For all FAST corners enable all optimizations except max DRCs
set_scenario_status *cFAST -all -max_transition false -max_capacitance false

report_scenarios

Corner PVT 결정

set_operating_conditions <ss0p95v125c>

pvt가 같거나 이름이 같은 등의 문제가 있을 때 → 직접 입력

set_process_number 0.99
set_voltage 0.75 -object_list VDD
set_voltage 0.95 -object_list VDDH
set_temperature 125

라벨링 하기

create_corner c_slow
set_process_number 1.0
set_voltage -object VDDG 0.9
set_temperature 125
create_scenario -name s_func_slow -mode m_func -corner c_slow

set_process_label -corner c_slow slow

report_pvt

Target Library Subset Example

# VA가 나뉘어 있을 때
set_target_library_subset -top {lib_HVT lib_SVT}
set_target_library_subset -objects Sub1/suba {lib_HVT lib_SVT lib_LVT}

# 쓰는 유닛이 섞여 있을 때
set_target_library_subset -objects {Sub2} -only_here {unit2_ref_lib/*}

OCV, AOCV, POCV

OCV : on-chip variation

PVT variation을 고려하여 유저가 직접 derate 값을 주는거

set_timing_Derate -late 1.04
set_timing_derate -early 0.92
  • 문제점 : 너무 정적(?) 유도리가 없어서 OCV로 타이밍 계산하면 칩이 안돌아감

AOCV : Advanced On-Ship Variation

systemic variation effects 고려, random variation 적용
그냥 aocv table 값 읽어오면 됨

set_app_options -list {
    time.aocvm_enable_analysis true
    time.ocvm_enabel_distance_analysis ture }
read_ocvm -corner SLOW SLOW_derate_table
read_ocvm -corner FAST FAST_derate_table

report_ocvm -type aocvm
  • 문제점 : ICC2는 GBA-based Analysis 하기 때문에 실제 패스 계산이 아닌 worst 계산하기 때문에 타이밍이 실제 패스가 아닐 수 있음

POCV : Parametric On-Chip Variation

delay 값을 평균에다가 표준편차의 합을 더해서 구함

set_app_options -name time.pocvm_enable_analysis -value true
set_app_options -name time.ocvm_enable_distance_analysis -value true

read_ocvm -corner SLOW SLOW_pocv_coefficient_file
read_ocvm -corner SLOw SLOW_pocv_distance_table

report_ocvm -type pocvm
report_timing -variation

# If LVF contains setup/hold constraint variation data
time.pocvm_enable_constraint_variation true

# If LVF contains output slew variation table
time.enable_slew_variation true

# Specify corner-specific sigmas 필요하면
set_pocvm_corner_sigma -corners {ff_corner} 4.0
report_ocvm -type pocvm -corner_sigma -corner ff_corner

LVF : Liberty Variation Format
Cell delay variation is modeled as a function of input transition and output load

더 필요한 설정을 찾고 싶으면
report_app_options time.*

Specify TLUplus Parasitic RC Models

# If the TLUplus models have not been loaded into a technology library,
# they can be loaded into the design library
# read_parasitic_tech -tlup $TLUPLUS_MAX_FILE -name maxTLU

# Specify the TLUplus model for each corner
# If the TLUplus models were loaded into the tech lib use the -library option
set_parasitic_parameters -coner c_slow -library ${techlib} -early_spec maxTLU -late_spec maxTLU
set_parasitic_parameters -coner c_fast \
    -library ${techlib} -early_spec minTLU -late_spec minTLU

Timing Reports with MCMM

  • report_timing : single worst setup timing path among all path groups of all active setup-enabled scenarios

  • report_timing -corners "C1 C4"
    report_timing -modes FUNC*
    report_timing -scenarios "S1 S2 S5 S6"
    : Report the single worst setup timing path from among the listed and active corners, modes or scenarios

  • report_timing -report_by corner|mode|scenario|group : worst setup timing path for each and every active corner, mode, scenario or path group

  • report_timing -report_by corner -corners "C1 C4"
    report_timing -report_by mode -modes FUNC*
    report_timing -report_by scenario -scenarios "S1 S2 S5 S6"
    : worst setup timing path for each listed and active corner, mode or scenario

set_app_options -list {
    time.delay_calculation_style zero_interconnect
    time.high_fanout_net_pin_capacitance 0pF
    time.high_fanout_net_threshold 100
}
update_timing -full
report_constraints -all_violators -max_delay
report_qor -summary -include setup
report_timing -slack_lesser than 0
profile
Myongji UNIV. B.S. in Electronic Engineering

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