[Verilator] Kogge-Stone Black Cell 구현

구현목표:

목적:
Kogge Stone 의 부품

저번과의 변동사항:
여러 모듈의 신속한 테스트를 위해 sim_main.cpp가 물리는 verilog 소스는 top.v로 통일시킴.
앞으로 top.v에서 각 모듈을 include 시킬 것.

//Black_Cell.v
module Black_Cell // Fully Combinatorial Circuit, NOT be CLOCKED
    (
        input P_j_i,
        input G_j_i,
        input P_k_j_plus_1,
        input G_k_j_plus_1,
        output P_k_i,
        output G_k_i
    );

    assign P_k_i = P_j_i & P_k_j_plus_1;
    assign G_k_i = (G_j_i &P_k_j_plus_1) | G_k_j_plus_1;

endmodule

// top.v
// DESCRIPTION: Verilator: Verilog example module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2017 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0

// See also https://verilator.org/guide/latest/examples.html"
`include "Black_Cell.v"

module top
   (
        input P_j_i,
        input G_j_i,
        input P_k_j_plus_1,
        input G_k_j_plus_1,
        output P_k_i,
        output G_k_i
   );
   Black_Cell blk1(
      .P_j_i(P_j_i),
      .G_j_i(G_j_i),
      .P_k_j_plus_1(P_k_j_plus_1),
      .G_k_j_plus_1(G_k_j_plus_1),
      .P_k_i(P_k_i),
      .G_k_i(G_k_i)
   );
endmodule

Makefile

######################################################################
#
# DESCRIPTION: Verilator Example: Small Makefile
#
# This calls the object directory makefile.  That allows the objects to
# be placed in the "current directory" which simplifies the Makefile.
#
# This file ONLY is placed under the Creative Commons Public Domain, for
# any use, without warranty, 2020 by Wilson Snyder.
# SPDX-License-Identifier: CC0-1.0
#
######################################################################
# Check for sanity to avoid later confusion

ifneq ($(words $(CURDIR)),1)
 $(error Unsupported: GNU Make cannot build in directories containing spaces, build elsewhere: '$(CURDIR)')
endif

######################################################################

# This is intended to be a minimal example.  Before copying this to start a
# real project, it is better to start with a more complete example,
# e.g. examples/make_tracing_c.

# If $VERILATOR_ROOT isn't in the environment, we assume it is part of a
# package install, and verilator is in your path. Otherwise find the
# binary relative to $VERILATOR_ROOT (such as when inside the git sources).
ifeq ($(VERILATOR_ROOT),)
VERILATOR = verilator
else
export VERILATOR_ROOT
VERILATOR = $(VERILATOR_ROOT)/bin/verilator
endif

MODULENAME = top
default:
	@echo "-- Verilator hello-world simple example"
	@echo "-- VERILATE & BUILD --------"
	$(VERILATOR) -cc --exe --build -j --trace $(MODULENAME).v sim_main.cpp
	@echo "-- RUN ---------------------"
	obj_dir/V$(MODULENAME)
	@echo "-- DONE --------------------"
	@echo "Note: Once this example is understood, see examples/make_tracing_c."
	@echo "Note: See also https://verilator.org/guide/latest/examples.html"

######################################################################

maintainer-copy::
clean mostlyclean distclean maintainer-clean::
	-rm -rf obj_dir *.log *.dmp *.vpd core

// sim_main.cpp
// DESCRIPTION: Verilator: Verilog example module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2017 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
//======================================================================

// Include common routines
#include <verilated.h>

#include <iostream>
using namespace std;

// Include model header, generated from Verilating "top.v"
#include "Vtop.h"
#include "verilated_vcd_c.h"

int main(int argc, char** argv, char** env) {
    // See a similar example walkthrough in the verilator manpage.

    // This is intended to be a minimal example.  Before copying this to start a
    // real project, it is better to start with a more complete example,
    // e.g. examples/c_tracing.

    // Prevent unused variable warnings
    if (false && argc && argv && env) {}

    // Construct the Verilated model, from Vtop.h generated from Verilating "top.v"
    Vtop* top = new Vtop;

    // FOR WAVEFORM
    Verilated::traceEverOn(true);
    VerilatedVcdC* wave_fp = new VerilatedVcdC;
    int time = 0;
    top->trace(wave_fp, 999);
    printf("waveform file name is top.vcd\n");
    wave_fp->open("./top.vcd");

    top->P_j_i=0;
    top->G_j_i=0;
    top->P_k_j_plus_1=0;
    top->G_k_j_plus_1=0;
    top->eval();
    wave_fp->dump(time); time++;

    top->P_j_i=0;
    top->G_j_i=0;
    top->P_k_j_plus_1=0;
    top->G_k_j_plus_1=0;
    top->eval();
    wave_fp->dump(time); time++;


    for(int i=0;i<16;i++){
        printf("i == %d => %d %d %d %d\n", i, i&(int)1, i&(int)2, i&(int)4, i&(int)8);
        top->P_j_i=(bool)(i&(int)1);
        top->G_j_i=(bool)(i&(int)2);
        top->P_k_j_plus_1=(bool)(i&(int)4);
        top->G_k_j_plus_1=(bool)(i&(int)8);
        top->eval();
        wave_fp->dump(time); time++;
    }

    // Final model cleanup
    top->final();
    wave_fp->close();

    // Destroy model
    delete top;

    delete wave_fp;
    // Return good completion status
    return 0;
}

결과

profit