졸프Project

1.[Verilator] Sint16_adder 구현

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2.[Verilator] Kogge-Stone Black Cell 구현

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3.현재 졸업프로젝트 목표

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4.fp32 Adder 알고리즘 검증코드

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5.FPU fp32 Multiplier 알고리즘 검증코드

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6.FPU fp32 Multiplier 알고리즘 검증코드_개선

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7.[심득사항] Debugging Procedure

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9.50MHz CLK에서 BaudRate 표

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