기존의 VecShiftRegister와 거의 다른 점이 없어서, 금방 풀었다.
// See LICENSE.txt for license details.
package problems
import chisel3.iotesters.PeekPokeTester
class VecShiftRegisterParamTests(c: VecShiftRegisterParam) extends PeekPokeTester(c) {
val reg = Array.fill(c.n){ 0 }
for (t <- 0 until 16) {
val in = rnd.nextInt(1 << c.w)
poke(c.io.in, in)
step(1)
for (i <- c.n-1 to 1 by -1)
reg(i) = reg(i-1)
reg(0) = in
expect(c.io.out, reg(c.n-1))
}
}
// See LICENSE.txt for license details.
package problems
import chisel3._
// Problem:
//
// Implement a parametrized simple shift register.
// 'n' is the number of elements in the shift register.
// 'w' is the width of one element.
class VecShiftRegisterParam(val n: Int, val w: Int) extends Module {
val io = IO(new Bundle {
val in = Input(UInt(w.W))
val out = Output(UInt(w.W))
})
// Implement below ----------
val shift_reg = Reg(Vec(n, UInt(w.W)))
for(i <- 1 until n){
shift_reg(i) := shift_reg(i-1)
}
shift_reg(0) := io.in
io.out := shift_reg(n)
}
// Implement above ----------
Exception이 제일 까다롭다..
어디서 에러가 떴는지 정확하게 짚어주지 않는다.
대충 이런 아주 긴 Excpetion이 나왔다.
info] Loading project definition from /home/user/Documents/chisel-tutorial/project
[info] Loading settings for project chisel-tutorial from build.sbt ...
[info] Set current project to chisel-tutorial (in build file:/home/user/Documents/chisel-tutorial/)
[info] sbt server started at local:///home/user/.sbt/1.0/server/f9829f7299b4fd9cac4a/sock
sbt:chisel-tutorial> test:runMain problems.Launcher VecShiftRegisterParam
[info] Compiling 1 Scala source to /home/user/Documents/chisel-tutorial/target/scala-2.12/classes ...
[warn] Multiple main classes detected. Run 'show discoveredMainClasses' to see the list
[info] running problems.Launcher VecShiftRegisterParam
Starting tutorial VecShiftRegisterParam
[info] [0.001] Elaborating design...
chisel3.internal.ChiselException: Exception thrown when elaborating ChiselGeneratorAnnotation
at chisel3.stage.ChiselGeneratorAnnotation.elaborate(ChiselAnnotations.scala:55)
at chisel3.stage.phases.Elaborate.$anonfun$transform$1(Elaborate.scala:19)
at scala.collection.TraversableLike.$anonfun$flatMap$1(TraversableLike.scala:245)
at scala.collection.immutable.List.foreach(List.scala:392)
at scala.collection.TraversableLike.flatMap(TraversableLike.scala:245)
at scala.collection.TraversableLike.flatMap$(TraversableLike.scala:242)
at scala.collection.immutable.List.flatMap(List.scala:355)
at chisel3.stage.phases.Elaborate.transform(Elaborate.scala:18)
at chisel3.iotesters.setupTreadleBackend$.apply(TreadleBackend.scala:143)
at chisel3.iotesters.Driver$.$anonfun$execute$2(Driver.scala:53)
at scala.runtime.java8.JFunction0$mcZ$sp.apply(JFunction0$mcZ$sp.java:23)
at logger.Logger$.$anonfun$makeScope$2(Logger.scala:168)
at scala.util.DynamicVariable.withValue(DynamicVariable.scala:62)
at logger.Logger$.makeScope(Logger.scala:166)
at logger.Logger$.makeScope(Logger.scala:127)
at chisel3.iotesters.Driver$.$anonfun$execute$1(Driver.scala:38)
at scala.runtime.java8.JFunction0$mcZ$sp.apply(JFunction0$mcZ$sp.java:23)
at scala.util.DynamicVariable.withValue(DynamicVariable.scala:62)
at chisel3.iotesters.Driver$.execute(Driver.scala:38)
at problems.Launcher$.$anonfun$tests$16(Launcher.scala:37)
at problems.Launcher$.$anonfun$tests$16$adapted(Launcher.scala:35)
at utils.TutorialRunner$.$anonfun$apply$3(TutorialRunner.scala:56)
at scala.collection.immutable.List.foreach(List.scala:392)
at utils.TutorialRunner$.apply(TutorialRunner.scala:47)
at problems.Launcher$.main(Launcher.scala:104)
at problems.Launcher.main(Launcher.scala)
at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at sun.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:62)
at sun.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.lang.reflect.Method.invoke(Method.java:498)
at sbt.Run.invokeMain(Run.scala:115)
at sbt.Run.execute$1(Run.scala:79)
at sbt.Run.$anonfun$runWithLoader$3(Run.scala:84)
at scala.runtime.java8.JFunction0$mcV$sp.apply(JFunction0$mcV$sp.java:23)
at scala.util.Try$.apply(Try.scala:213)
at sbt.Run.directExecute$1(Run.scala:84)
at sbt.Run.runWithLoader(Run.scala:93)
at sbt.Defaults$.$anonfun$bgRunMainTask$7(Defaults.scala:1458)
at scala.runtime.java8.JFunction0$mcV$sp.apply(JFunction0$mcV$sp.java:23)
at scala.util.Try$.apply(Try.scala:213)
at sbt.internal.BackgroundThreadPool$BackgroundRunnable.run(DefaultBackgroundJobService.scala:360)
at java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1149)
at java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:624)
at java.lang.Thread.run(Thread.java:750)
Caused by: java.lang.IndexOutOfBoundsException: 8
at scala.collection.immutable.Vector.checkRangeConvert(Vector.scala:127)
at scala.collection.immutable.Vector.apply(Vector.scala:118)
at chisel3.Vec.apply(Aggregate.scala:251)
at problems.VecShiftRegisterParam.<init>(VecShiftRegisterParam.scala:24)
at problems.Launcher$.$anonfun$tests$17(Launcher.scala:36)
at chisel3.Module$.do_apply(Module.scala:52)
at chisel3.stage.ChiselGeneratorAnnotation.$anonfun$elaborate$1(ChiselAnnotations.scala:50)
at chisel3.internal.Builder$.$anonfun$build$1(Builder.scala:408)
at scala.util.DynamicVariable.withValue(DynamicVariable.scala:62)
at chisel3.internal.Builder$.build(Builder.scala:406)
at chisel3.stage.ChiselGeneratorAnnotation.elaborate(ChiselAnnotations.scala:50)
... 43 more
================================================================================
Errors: 1: in the following tutorials
Tutorial VecShiftRegisterParam: exception Exception thrown when elaborating ChiselGeneratorAnnotation
================================================================================
2023-08-08 17:46:52,163 shutdown-hooks-run-all ERROR No Log4j 2 configuration file found. Using default configuration (logging only errors to the console), or user programmatically provided configurations. Set system property 'log4j2.debug' to show Log4j 2 internal initialization logging. See https://logging.apache.org/log4j/2.x/manual/configuration.html for instructions on how to configure Log4j 2
// See LICENSE.txt for license details.
package problems
import chisel3._
// Problem:
//
// Implement a parametrized simple shift register.
// 'n' is the number of elements in the shift register.
// 'w' is the width of one element.
class VecShiftRegisterParam(val n: Int, val w: Int) extends Module {
val io = IO(new Bundle {
val in = Input(UInt(w.W))
val out = Output(UInt(w.W))
})
// Implement below ----------
val shift_reg = Reg(Vec(n, UInt(w.W)))
for(i <- 1 until n){
shift_reg(i) := shift_reg(i-1)
}
shift_reg(0) := io.in
io.out := shift_reg(n-1)
}
// Implement above ----------
reg의 index를 n-1로 정정하였고, 통과했다.