[ucb-bar chisel-tutorial] Multiple Clock Multiple Reset

Chisel 코드. 명시적으로 Multiple Clock과 Reset을 지정할 수 있다.
기본은 Sync Reset이며,
clock은 추가적으로 Input선언시 Bool보다 Clock()이라는 선언을 해줘야 하며,
Reset은 따로 필요없이 Bool로 Input해주면 된다.

// we need to import multi-clock features
import chisel3.experimental.{withClock, withReset, withClockAndReset}

class ClockExamples extends Module {
  val io = IO(new Bundle {
    val in = Input(UInt(10.W))
    val alternateReset    = Input(Bool())
    val alternateClock    = Input(Clock())
    val outImplicit       = Output(UInt())
    val outAlternateReset = Output(UInt())
    val outAlternateClock = Output(UInt())
    val outAlternateBoth  = Output(UInt())
  })

  val imp = RegInit(0.U(10.W))
  imp := io.in
  io.outImplicit := imp

  withReset(io.alternateReset) {
    // everything in this scope with have alternateReset as the reset
    val altRst = RegInit(0.U(10.W))
    altRst := io.in
    io.outAlternateReset := altRst
  }

  withClock(io.alternateClock) {
    val altClk = RegInit(0.U(10.W))
    altClk := io.in
    io.outAlternateClock := altClk
  }

  withClockAndReset(io.alternateClock, io.alternateReset) {
    val alt = RegInit(0.U(10.W))
    alt := io.in
    io.outAlternateBoth := alt
  }
}

println(getVerilog(new ClockExamples))

변환결과

module ClockExamples(
  input        clock,
  input        reset,
  input  [9:0] io_in,
  input        io_alternateReset,
  input        io_alternateClock,
  output [9:0] io_outImplicit,
  output [9:0] io_outAlternateReset,
  output [9:0] io_outAlternateClock,
  output [9:0] io_outAlternateBoth
);
  reg [9:0] imp; // @[cmd29.sc 14:20]
  reg [9:0] REG; // @[cmd29.sc 20:25]
  reg [9:0] REG_1; // @[cmd29.sc 26:25]
  reg [9:0] REG_2; // @[cmd29.sc 32:22]
  assign io_outImplicit = imp; // @[cmd29.sc 16:18]
  assign io_outAlternateReset = REG; // @[cmd29.sc 22:26]
  assign io_outAlternateClock = REG_1; // @[cmd29.sc 28:26]
  assign io_outAlternateBoth = REG_2; // @[cmd29.sc 34:25]
  always @(posedge clock) begin
    if (reset) begin // @[cmd29.sc 14:20]
      imp <= 10'h0; // @[cmd29.sc 14:20]
    end else begin
      imp <= io_in; // @[cmd29.sc 15:7]
    end
    if (io_alternateReset) begin // @[cmd29.sc 20:25]
      REG <= 10'h0; // @[cmd29.sc 20:25]
    end else begin
      REG <= io_in; // @[cmd29.sc 21:12]
    end
  end
  always @(posedge io_alternateClock) begin
    if (reset) begin // @[cmd29.sc 26:25]
      REG_1 <= 10'h0; // @[cmd29.sc 26:25]
    end else begin
      REG_1 <= io_in; // @[cmd29.sc 27:12]
    end
    if (io_alternateReset) begin // @[cmd29.sc 32:22]
      REG_2 <= 10'h0; // @[cmd29.sc 32:22]
    end else begin
      REG_2 <= io_in; // @[cmd29.sc 33:9]
    end
  end
endmodule